Cuttle Cart 2 Technical Specs Copyright 2004 - Chad Schell The Cuttle Cart 2 consists of three primary chips: PSD - The boot controller, 256K of Primary Flash RAM, 32K of Second Flash RAM, and 4K of NVRAM. This chip controls the CC2 at boot up, and handles such tasks as communicating with the MMC and programming the FPGA. FPGA - The reconfigurable bankswitching controller. Also used to implement the serial port for serial communications. 512K SRAM - General purpose XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX PSD: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX This section describes the aspects of the PSD. These are non-volatile and non-reprogrammable features and mappings. PSD Control Registers: These registers allow access to the FPGA, MMC, and memory control registers. The registers are available from $0600-$06FF or when the csiop_cs input signal is pulled low. The $0600-$06FF mode is the default boot up mode. csiop_cs is an FPGA generated signal that allows the registers to be made available in any desired memory location $xx00-$xxFF. (Obviously the location must be chosen so as not to conflict with other active devices.) All register locations are an offset into the active Register Window. MMC/FPGA - Offset $20 Writing to this address communicates with either the MMC or the FPGA. (They are seleted by chip select bits in other registers.) Writing to this address activates a byte exchange. The value written to the register is transfered into the MMC or FPGA. The FPGA is write only, but the MMC simultaneously transmits a byte that is stored in this register after the transfer is completed. The value is held in the register and can be read at any time prior to the next write to this register. Note that MMC/FPGA communications require 8 6502 clock cycles to complete. No reads or writes to this register should be performed within 8 clock cycles of writing to it. Page Register - Offset $E0 Used to select which Flash RAM pages are active, to control handshaking between the FPGA and the Boot Controller, and to enable the NVRAM. Bits 0-3: Bank Selection Bit 4: HSC_EN Enables HSC section of NVRAM - Active High Bit 5: NVRAM_EN Enables Remainder of NVRAM (user settings) - Active High Bit 6: FPGA_CS Enables FPGA programming clk - Active High Bit 7: FPGA_GO Transfer CC2 Control from PSD to FPGA - Active High The PSD communicates with the CC2 by means of three multipurpose IO registers, B, C, and D. These registers are accessed and controlled by Direction, Drive Select, Input, and Output Registers. Here is a list of the signals connected on each port, and the type of signal. Only ports labeled I, O, or I/O should be modified by the user in code running on the 6502. PSD B Register: Bit # Signal Type: Notes: 0 MMC_OUT Input Reg Output from MMC to PSD 1 FPGA_REQ Logic In Used by FPGA to access PSD after FPGA_GO is High 2 CSIOP_CS Logic In PSD Registers Respond to all addresses when Low 3 FPGA_CLK Comb O = MMC_CLK & FPGA_CS 4 FPGA_PROGRAM I/O 5 FPGA_INIT I/O Must be set to Open Collector in input mode 6 FPGA_DONE I 7 MMC_IN_OUT Output Reg Output from PSD to MMC PSD C Register: Bit # Signal Direction Notes: 0 TMS X JTAG 1 TCK X JTAG 2 VSTBY X Battery Power 3 - X 4 MMC_CS_OUT O Active Low 5 TDI X JTAG 6 TDO X JTAG 7 MMC_CLK_OUT Clk Out Runs for 8 cycles after MMC Reg written PSD D Register: Bit # Signal Direction Notes: 0 FPGA_GO Chip Select Active High, Controlled by FPGA_GO in Page Register (Must be set to output in direction register) 1 RAM_CE O Active Low 2 POKEY_CS O Active High PSD I/O Register Offsets used by CC2: Register Name Offset Input B $01 Output B $05 Output C $12 Output D $13 Direction B $07 Drive Select B $09 Direction C $14 Direction D $15 PSD Power Management Register - Offset $b0 Used to set the PSD into low power mode by disabling it's TURBO bit. 7800 is so slow that TURBO is NOT necessary. PSD Memory System The PSD provides the CC2 with FLASH ROM and NVRAM. The addressing schemes for these memories is fixed at prodution time and cannot be altered. 4K of Battery Backed Ram: 2K Used for High Score Cart Emulation: Located from $1000-$17FF if HSC_EN & fpga_req & csiop_cs 2K used for storing user settings: Located from $800-$FFF if NVRAM_EN & fpga_req & csiop_cs 256K Primary Flash RAM: Split into 8 pages of 32K each. Atari address lines A0-A14 are attached directly to A0-A14 of the flash RAM. So when less than 32K of a page is mapped into Atari address space, the portion of the page available is determined by A0-A14. In the table below Page # refers to the physical Flash RAM page. Address range refers to the address in the Atari memory map at which the page is available. Bank Selection refers to that must be set in the Bank Selection bits of the PSD Page Register. Additional Enables are additional conditions which must be met for the page to be active. See elsewhere in this manual for a description of these signals. Page # Address Range Bank Selection Additional Enables 0 $8000-$FFFF 0 !FPGA_GO & !emg_boot & csiop_cs 0 $8000-$FFFF 1 !FPGA_GO & emg_boot & csiop_cs Note: Page 0 is the boot page. The menu mode is contained in this page. 1 $8000-$FFFF 1 !FPGA_GO & !emg_boot & csiop_cs 1 $8000-$FFFF 2 !FPGA_GO & emg_boot & csiop_cs Note: Page 1 contains the dev mode code. Note: Pages 2-7 are currently unused. 2 $8000-$FFFF 2 !FPGA_GO & !emg_boot & csiop_cs 2 $8000-$FFFF 3 !FPGA_GO & emg_boot & csiop_cs 2 $3000-$3FFF 9 !FPGA_GO & !emg_boot & csiop_cs 3 $8000-$FFFF 3 !FPGA_GO & !emg_boot & csiop_cs 3 $8000-$FFFF 4 !FPGA_GO & emg_boot & csiop_cs 3 $4000-$7FFF 10 !FPGA_GO & !emg_boot & csiop_cs 4 $8000-$FFFF 4 !FPGA_GO & !emg_boot & csiop_cs 4 $8000-$FFFF 5 !FPGA_GO & emg_boot & csiop_cs 4 $3000-$3FFF 11 !emg_boot & fpga_req & csiop_cs 5 $8000-$FFFF 5 !FPGA_GO & !emg_boot & csiop_cs 5 $8000-$FFFF 6 !FPGA_GO & emg_boot & csiop_cs 5 $4000-$7FFF 12 !emg_boot & fpga_req & csiop_cs 6 $8000-$FFFF 6 !FPGA_GO & !emg_boot & csiop_cs 6 $8000-$FFFF 7 !FPGA_GO & emg_boot & csiop_cs 6 $8000-$FFFF 13 !emg_boot & fpga_req & csiop_cs 7 $8000-$FFFF 7 !FPGA_GO & !emg_boot & csiop_cs 7 $8000-$FFFF 8 !FPGA_GO & emg_boot & csiop_cs 32K Secondary Flash RAM: The emergency boot system RAM. Accessible as follows: Page # Address Range Bank Selection Additional Enables 0 $8000-$FFFF 0 !FPGA_GO & emg_boot & csiop_cs 8 $8000-$FFFF 1 !FPGA_GO & !emg_boot & csiop_cs The code and data stored in the FLASH RAM (both primary and secondary) is field upgradable. (The OS can be updated by the end user.) XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX FPGA: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX The FPGA is the primary mechanism of provided flexibility in the CC2. It has complete control over access to the 512K of general purpose SRAM. While the PSD is running things (OS mode) the FPGA acts as a slave to the PSD, providing access to the SRAM for loading games as well as serial port functionality. This is accomplished through a default FPGA configuration that is stored in the PSD flash RAM as part of the OS code. In order to run a game, the PSD reprograms the FPGA with the appropriate bankswitching code and then hands control over the FPGA. Once the FPGA has control, it can still access the PSD and the MMC (by going through the PSD.) This section will NOT cover the various game bankswitching methods, but will describe the default FPGA OS mode, and the communication/handoff methods between the FPGA and the PSD. What the FPGA Controls: SRAM Address Lines A0-A18. SRAM CE (PSD also controls SRAM CE - both must be enabled to use SRAM) SRAM OE - SRAM output enable SRAM WE - SRAM write enable SERIAL_OUT - Output pin on Audio Jack (nominally used for serial comms) POKEY CE (PSD also controls POKEY CE - both must be enabled to use POKEY) FPGA_REQ (Requests access to PSD NVRAM after FPGA has control) CSIOP_CS (Requests access to PSD Control Registers after FPGA has control) DATA Output - FPGA can put data on the bus. (Doesn't control the data bus though, must make sure to avoid contention with other parts.) IRQ - 7800 Interrupt Request Line What the FPGA can read: SERIAL_IN - Input pin on Audio Jack (nominally used for serial comms) POKEY_IRQ - Interrupt Requests from POKEY 7800 Address Lines A0-A15 - 7800 Address Bus 7800 Data Lines D0-D7 - 7800 Data Bus 7800 Clk2 - 7800 Clock 7800 R/W - 7800 R/W line 7800 HALT - Input from 7800 that says CPU is halted FPGA_GO - PSD signal that FPGA is in control Programming the FPGA: The FPGA in the CC2 is an SRAM based FPGA. There is no limit to the number of times it can be reprogrammed, but it does not retain any programming once power has been removed from the CC2. The FPGA must be programmed by the PSD. The PSD does this initially from code stored in the PSD's FLASH RAM as part of the boot up sequence. When a game is ready to be run the PSD reprograms the FPGA with code stored in a bankswitching file located on the MMC. Specific details of the programming protocol are not provided in this guide. See the OS source code for details. Handing control over to the FPGA: To hand control over the FPGA, a section of source code must run from outside the PSD, typically from RAM inside the 7800 itself. (Running from CC2 SRAM would require careful logic in the bankswitching code.) Control is handed off by setting the FPGA_GO bit in the PSD Page Register. Once this bit is set high, PSD FLASH RAM will no long respond to any addresses, so all OS code will no longer be accessible to the 7800. PSD NVRAM will respond if the appropriate HSC_EN or NVRAM_EN bits are also set in the PSG Page Register. The MMC and FPGA CS bits should be disabled before handing control over to the FPGA. Accessing the PSD and MMC after the FPGA has control: The FPGA can still access the PSD after the FPGA_GO bit has been set. NVRAM can be accessed if HSC_EN or NVRAM_EN have been set in the PSD Page Register by setting the FPGA_REQ bit high. See the PSD memory section for details on the addresses where these two memory sections are available. The PSD control registers can be accessed by setting the CSIOP_CS line low. This will make the control registers active REGARDLESS of the address. In order to have access to any of these control lines, the logic for setting them must be built into the bankswitching method programmed into the FPGA. This is how CSIOP_CS can be used safely. The FPGA logic will limit the address range during which CSIOP_CS is low. Default FPGA Mode (OS Mode): This section presents the details of the default OS mode programmed into the FPGA at boot time. SRAM Access: SRAM responds to read/write access in two windows in the 7800 address map: $4000-$7FFF Used for loading game code $3800-$3FFF Used to shadow the screen font The SRAM in the $4000-$7FFF window is accessed in banks of 16K, where the 16K bank in use is selected by writing the bank number to $0510. Valid bank numbers are from 0 to 32. The SRAM in the $3800-$3FFF window always points to the last 2K of the SRAM. This window exists to create a shadow copy of the onscreen FONT. Unfortunately the 7800 does NOT properly control the clock line during DMA transfers (the data is being fetched faster than the clock). The PSD requires a proper clock to line function correctly, so FONT retrieval from the PSD does not function will on some 7800s, resulting in a lot of video noise and a generally ugly (but otherwise harmless) display. The snow would appear when the TIA was accessed to read the console and joystick buttons. To fix this problem the FONT was shadowed to the general SRAM which does not require the clock for read access. Note that SRAM access is controlled by both the FPGA and the PSD. In order to access the SRAM the RAM_CE bit on the PSD must be set low. (This is always true, be sure to set RAM_CE low before running a game!!!) POKEY Access: The POKEY responds to the address range $0500 $050F. Note that POKEY access is controlled by both the FPGA and the PSD. In order to access the POKEY the POKEY_CS bit on the PSD must be set high. (This is always true, be sure to set the POKEY_CS high before running a game that uses the POKEY!!! It it always safe to set it high before running any game as the FPGA will still control whether or not it is used.) Serial Port: The FPGA in OS mode emulates an RS-232 serial port. It provides a 16 byte circular RX buffer and a 1 byte TX Buffer (in addition to the shift register of data currently being transmitted). Serial Port Addresses: Serial Baud $0511 Write a timer value to this address to set the baud rate. Writing to this port also clears both TX and RX buffers and the serial status register. Any bytes currently being transmitted or received will be dropped. (In other words it resets the serial port.) Here are suggested baud rate timer values: Baud Rate NTSC Timer Value PAL Timer Value 9600 186 185 14400 124 123 19200 93 92 38400 46 46 57600 30 30 115200 15 15 Serial Data $0512 Write this address to transmit a byte. If the TX buffer is full the write will be ignored and the TX_OVERFLOW bit will be set. The bit currently in the TX buffer will be transmitted normally. Read this address to receive first byte off RX Buffer. Serial Status $0513 Read this to receive the serial status byte Write any value to it to clear the ERROR bits. (But not the ready bits.) The format of the status byte is as follows: Bit # Name Description: 0 - Always 0 1 - Always 0 2 - Always 0 3 Frame Error An RX frame error occurred 4 RX Overflow Error The RX buffer is has overflowed. The oldest 16 bytes are in the buffer. The newest data has been dropped. 5 TX Overflow Error An attempt was made to overwrite the full TX Buffer. 6 TX Buffer Full The TX buffer is full (Don't write to it!) 7 RX Data Ready A byte is ready for reading. To use the serial port, set the baud rate and then monitor the status byte. When RX Data Ready is set, read the byte and process it. If you are transmitting, wait until TX Buffer Full goes low before writing a new byte into the TX Buffer. Because the TX buffer is separate from theTX shift register it is possible to maintain an continuous serial TX stream. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX SRAM: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX The SRAM is simply 512K of general purpose SRAM. It is controlled predominately by the FPGA. See the FPGA section for details. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX POKEY: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX The CC2 has a POKEY socket onboard. A POKEY can be installed to provide POKEY sounds to games that use it. Access to the POKEY is controlled predominately by the FPGA. See the FPGA section for details. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX MMC: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX The MMC is used to store game, bankswitching, and startup code data. The MMC is controlled entirely by the PSD. Currently the CC2 OS provides READ ONLY access to FAT16 formatted MMCs. Write access is possible if the proper FAT routines are created. XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Game Start Sequence: XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Starting game requires three files off the MMC, and three steps. Step 1: Read the game binary off the MMC and load it into the CC2 SRAM. Step 2: Read the FPGA bankswitching configuration file off the MMC and configure the FPGA. This must be done second as the ability to write to SRAM will now be in game mode instead of OS mode. Step 3: Read the startup code file off the MMC into 7800 RAM. This code should handles the change of control from the PSD to the FPGA. Once loaded jump to this code and run it.