Artoj

I finally figured out the chip that should be correct, amazing enough after double checking it was just a 1024x4 TMS2114, I don't know where Peter got those numbers on the sheet, I am guessing it was a supplier part number not the manufacturers actual part number. The DSR EPROM is the greatest problem at the moment, I found a few of the old printed listing for the DSR, it looks like it has many parts, as the PIO/RS232 is a separate program segment than the Floppy DSR. I have redesigned the PIO so it matches the complete IBM PIO as shown, I added 2 more chips and the DSR must be modified as well. Regards Arto PIO - IBM standard Pin Register Direction Signal 1 Control 0 I/O Strobe 2 Data 0 I/O DB0 3 Data 1 I/O DB1 4 Data 2 I/O DB2 5 Data 3 I/O DB3 6 Data 4 I/O DB4 7 Data 5 I/O DB5 8 Data 6 I/O DB6 9 Data 7 I/O DB7 10 Status 6 IN Acknowledge 11 Status 7 IN Busy 12 Status 5 IN Paper Out/End 13 Status 4 IN Select 14 Control 1 I/O Auto Linefeed 15 Status 3 IN Error 16 Control 2 I/O Initialise 17 Control 3 I/O Select Printer 18 Ground 19 Ground 20 Ground 21 Ground 22 Ground 23 Ground 24 Ground 25 Ground

Thanks, I always need to do more reading (LOL, I read the reviews ), i have quite a lot of computer books and I think they reference Knuth, it looks like a good read, I will be getting a copy at some point. Ternary computing has been more an Art form for me rather than one of Electrical or Computer Engineering, I arrived at its implications through the study of the natural world (as an Artist) and it's hidden arithmetic (Harmony of proportions, Magic squares, Fibonacci etc) where 3 is a closer approximation to 2.718 than 2 (natural growth e, the base of natural logarithms). Regards Arto.

TI99 Mini Mega Ram V2 The first version was in 1986 in a sketch I made and how I could address a very large RAM. I have only recently revised my methodology and I will revert back to the original ideas it when this current system has been proven and it works. The final object is to address at least 4GB of RAM, by adding another 8 bits to this address bus set up. I have separated the read address and read data and the write address and data, so you can easily do copy and move functions without losing track of your address location. The great thing is you can do all this in BASIC as well. CALL LOAD(-27904,ADRESSA) A0 A1 A2 A3 A4 A5 A6 A7 CALL LOAD(-27903,ADRESSB) A8 A9 A10 A11 A1 A13 A14 A15 CALL LOAD(-27902,ADRESSC) A16 A17 A18 A19 A20 A21 A22 A23 CALL LOAD(-27901,DATAOUT) 8 BIT BYTE CALL LOAD(-27900,ADRESSA) A0 A1 A2 A3 A4 A5 A6 A7 CALL LOAD(-27899,ADRESSB) A8 A9 A10 A11 A1 A13 A14 A15 CALL LOAD(-27898,ADRESSC) A16 A17 A18 A19 A20 A21 A22 A23 CALL PEEK(-27897,DATAIN) 8 BIT BYTE The scheme here is to prove the 24 bit bus system then expand it to 32 bit addressing. The original (86) scheme used far less chips and directly addressed one large chip. This version can address 16mb of static RAM, with a possibility of adding battery backup on another version. If I added battery backup to each module, you could swap out the module as a portable memory storage. The only change would be the module and not the main board, a home made SD Ram card if you like. I made it this way so you I could design different modules from different sources, as a lot of the 2Meg static RAM chips have different pin-outs, while the prices were another consideration as well. Depending how keen you are, there is a provision to add 3 more boards to give you a total of 64 Megabytes of RAM!, you might have to beef up the power supply to do this though. These incursions into memory systems was made so I could apply ternary logic to standard static RAM. This is my final goal, once achieved, I think a Ternary CPU will be the next logical step. I will be making small Kits at some point for my different TI projects and a Ternary Relay Primer Kit is being assembled at present. Thank you for all your encouragement in these endeavours, regards Arto. MSB LSB ADDRESS 11 1111 1111 2222 0123 4567 8901 2345 6789 0123 ADRT1 >9300 ADDRESS------>0 0 0 BITS FOR DATA OUT 1111 1111 0000 0000 0000 0000 ADRT2 >9301 ----------------^ ^ 0000 0000 1111 1111 0000 0000 ADRT3 >9302 ------------------! 0000 0000 0000 0000 1111 1111 DTAUT >9303 DATA BYTE OUT 8 BITS ADRN1 >9304 ADDRESS------>0 0 0 BITS FOR DATA IN 1111 1111 0000 0000 0000 0000 ADRN2 >9305 ----------------^ ^ 0000 0000 1111 1111 0000 0000 ADRN3 >9306 ------------------! 0000 0000 0000 0000 1111 1111 DTAIN >9307 DATA BYTE IN 8 BITS ************************************************************************************************************ DATA1 >48 72 H DATA2 >45 69 E DATA3 >4C 76 L DATA5 >4C 79 O READB BSS 32 FILLING ADDRESS >0FF000 TO >0FF004 WITH "HELLO" 0000 1111 1111 0000 0000 0000 BANK RAM 1 AS A WORD MOVE LI R0,>0FF0 SET MSB LI R1,>0048 SET LSB + BYTE "H" LI R2,>0145 SET LSB + BYTE "E" LI R3,>024C LI R4,>034C LI R5,>044F MOV R0,@ADRT1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO WRITE (WORD) MOV R1,@ADRT3 LOAD LSB + DATA TO SEND ADDRESS TO LATCHES THEN WRITE DATA TO RAM (WORD) MOV R0,@ADRT1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO WRITE (WORD) MOV R2,@ADRT3 LOAD MSB + DATA TO SEND ADDRESS TO LATCHES THEN WRITE DATA TO RAM (WORD) MOV R0,@ADRT1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO WRITE (WORD) MOV R3,@ADRT3 LOAD LSB + DATA TO SEND ADDRESS TO LATCHES THEN WRITE DATA TO RAM (WORD) MOV R0,@ADRT1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO WRITE (WORD) MOV R4,@ADRT3 LOAD LSB + DATA TO SEND ADDRESS TO LATCHES THEN WRITE DATA TO RAM (WORD) MOV R0,@ADRT1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO WRITE (WORD) MOV R5,@ADRT3 LOAD LSB + DATA TO SEND ADDRESS TO LATCHES THEN WRITE DATA TO RAM (WORD) READING BACK FROM THE SAME ADDRESS LI R0,>0FF0 SET MSB LI R1,>0000 SET LSB + CLEAR DATA BYTE LI R2,>0100 SET LSB + CLEAR DATA BYTE LI R3,>0200 SET LSB + CLEAR DATA BYTE LI R4,>0400 SET LSB + CLEAR DATA BYTE LI R5,>0500 SET LSB + CLEAR DATA BYTE MOV R0,@ADRN1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO READ (WORD) MOVB R1,@ADRN3 LOAD LSB TO SEND ADDRESS TO LATCHES READY TO READ (BYTE) MOVB @DTAIN,@READB READ BYTE (BYTE) MOV R0,@ADRN1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO READ MOVB R2,@ADRN3 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO READ MOVB @DTAIN,@READB+1 READ BYTE MOV R0,@ADRN1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO READ MOVB R3,@ADRN3 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO READ MOVB @DTAIN,@READB+2 READ BYTE MOV R0,@ADRN1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO READ MOVB R4,@ADRN3 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO READ MOVB @DTAIN,@READB+3 READ BYTE MOV R0,@ADRN1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO READ MOVB R5,@ADRN3 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO READ MOVB @DTAIN,@READB+4 READ BYTE

Hi All, While my workshop is in disarray, my creativity has never been sharper, I decided to look at the MPBII card and create a Mini Card version. I have made the digital ports 8 bit and made 4 instead off 2, other wise it is much the same design, besides being usable to a basic console with just 32k and XB. The other card is for testing the ADC with a trim-pot and the digital outputs with leds. I will write software at some point, as I do not have the CLOCK program. Listed below is the memory usage of the card. Regards Arto. TI99/4A Digitizer and Clock --------------------------- Circuit based on the MPBII ADC input -0.1 to +5.1 volts 0.100 amps max Data Range 0 to 255 Allow 100 Micro Seconds for conversion ---------------------------------------------------------------------------------------- DIGITAL INPUTS -------------- PIN 1 2 3 4 5 6 7 8 DATA CN BIT 0 1 2 3 4 5 6 7 DIG A H2 >8600 8602 8604 8606 8608 860A 860C 860E -31232 -31230 -31228 -31226 -31224 -31222 -31220 -31218 DIG B H3 >86C0 86C2 86C4 86C6 86C8 86CA 86CC 86CE -31040 -31038 -31036 -31034 -31032 -31030 -31028 -31026 DIG C H4 >8700 8702 8704 8706 8708 870A 870C 870E -30976 -30974 -30972 -30970 -30968 -30966 -30964 -30962 DIG D H5 >8740 8742 8744 8746 8748 874A 874C 874E -30912 -30910 -30908 -30906 -30904 -30902 -30900 -30898 J5 >8780 -30848 J6 >87C0 -30784 CLOCK ----- DATA BYTES DESCRPIT MILS HTS S M H DW DM M COUNTER >8640 8642 8644 8646 8648 864A 864C 864E -31168 -31166 -31164 -31162 -31160 -31158 -31156 -31154 RAM >8650 8652 8654 8656 8658 865A 865C 865E -31152 -31150 -31148 -31146 -31144 -31142 -31140 -31138 DESCRPIT ST RG CN RG CR ST RM RST ST BIT GO CMD STN BY REGISTERS >8660 8662 8664 8666 8668 866A 866C XXXX -31136 -31134 -31132 -31130 -31128 -31126 -31124 ------ TEST MD >8670 XXXX XXXX XXXX XXXX XXXX XXXX 867E ----- ------ ----- ------ ------ ------ ------ -31106 ADC --- DATA BYTES NOT USED >8680 ------ DESCRPIT SCONV IN 7 IN 6 IN5 IN4 IN3 IN2 IN1 INPUT >8690 8692 8694 8696 8698 869A 869C 869E -31088 -31086 -31084 -31082 -31080 -31078 -31076 -31074 IN0 >86A0 XXXX -31072 ------ --------------------------------------------------- CLOCK ----- >8640 -31168 COUNTER MILLISECONDS >8642 -31166 HUNDREDTHS AND TENTHS >8644 -31164 SECONDS >8646 -31162 MINUTES >8648 -31160 HOURS >864A -31158 DAY OF THE WEEK >864C -31156 DAY OF THE MONTH >864E -31154 MONTH >8650 -31152 RAM MILLISECONDS >8652 -31150 HUNDREDTHS AND TENTHS >8654 -31148 SECONDS >8656 -31146 MINUTES >8658 -31144 HOURS >865A -31142 DAY OF THE WEEK >865C -31140 DAY OF THE MONTH >865E -31138 MONTH >8660 -31136 INTERRUPT STATUS REGISTER >8662 -31134 INTERRUPT CONTROL REGISTER >8664 -31132 COUNTERS RESET >8666 -31130 RAM RESET >8668 -31128 STATUS BIT >866A -31126 GO COMMAND >866C -31124 STANDBY INTERRUPT >866E -31122 NOT USED . " . " >867C -31108 NOT USED >867E -31106 TEST MODE ADC --- >8680 -31104 NOT USED . " . " >868E -31090 NOT USED >8690 -31088 START CONVERSION >8692 -31086 READ INPUT 7 >8694 -31084 READ INPUT 6 >8696 -31082 READ INPUT 5 >8698 -31080 READ INPUT 4 >869A -31078 READ INPUT 3 >869C -31076 READ INPUT 2 >869E -31074 READ INPUT 1 >86A0 -31072 READ INPUT 0 >86A2 -31070 NOT USED . " . " >86BE -31042 NOT USED DIGITAL OUTPUT H2 ----------------- HEX BASIC PIN 1234 5678 >8600 -31232 WRITE 8 BITS TO U13 0000|0000 >8602 -31230 COPY OF ABOVE . " , " >863E -31170 COPY OF ABOVE DIGITAL OUTPUT H3 ----------------- >86C0 -31040 WRITE 8 BITS TO U14 0000|0000 >86C2 -31038 COPY OF ABOVE . " . " >36FE -30978 COPY OF ABOVE DIGITAL OUTPUT H4 ----------------- >8700 -30976 WRITE 8 BITS TO U17 0000|0000 >8702 -30974 COPY OF ABOVE . " . " >873E -30914 COPY OF ABOVE DIGITAL OUTPUT H5 ----------------- >8740 -30912 WRITE 8 BITS TO U18 0000|0000 >8742 -30910 COPY OF ABOVE . " . " >877E -30850 COPY OF ABOVE OTHER PINS (future additions/tests) ---------- J1 +5V J2 GND J3 BAT +V J4 >8780 J5 >87C0 J6 RDBENA J7 A15

Hi All, I will add another thread later for my assembly routines I wrote back in the 80's but for now I will just put a link to my Wordpress page for the TI99. I have typed from a badly stained and faded printed copy the first of a long list of software I wrote in Assembly, this one is a Window that you can use to add text and graphics, regards Arto. https://artoheino.com/ti99-4a-hardware-and-software-creativity/?preview_id=1774&preview_nonce=6b74e3beaa&preview=true

Even though this is an old thread and someone might be interested in my untested design for a switchable (TI/ATARI) dual joy port. I will keep you posted when I have built it, regards Arto.

Hi All, As my workshop is being rebuilt and reorganised, I had to put all my projects on hold. Sadly I have not built any of my boards yet, still, I am finding a lot of partly finished projects from the 80's and early 90's. Here is one more project, that has not been tested yet. I found the software written on a crumbling sheet of paper, I vaguely remember writing it using the Mini Memory, so if anyone is interested in completing my work, here are my designs and the assembly code. I do not have a working TI at present, so I cannot even test it. The assembly here is verbatim from my hand written notes. I will eventually notate and explain the code. I am not sure the hardware matches the software, they were created at different times. Just snap off the Pen PCB from the main board and use a 2 wire lead to connect them. So have fun, regards Arto TI99/4A Light Pen -------------------- Using mini memory cartridge. CALL LINK("LITPEN",X,Y,C) START LWPI >70B8 MOV R11,R10 CI C9,>1234 JEQ CK LI R0.>07F8 LI R1,DF LI R2,8 BLWP @>6028 LI R0,>0799 LI R1,>FF00 BLWP @VSBW LI R9,>1234 LI R4,>0606 CK LI R12,>24 LDCR R4,3 LI R12,6 STCR R5,5 - PRESS L/R SLA R5,6 | PRESS LITPEN JNE EX - BUTTON CLR R5 CLR R0 LI R3,>FF00 LI R13,768 CLR R6 LP BLWP @VSBR MOVB R1,R6 MOVB R3,R1 BLWP @VSBW CLR R4 LI R8,64 L2 STCR R5,5 SLA R5,4 JNC L3 AI R4,1 L3 DEC R8 JNE L2 MOVB R6,R1 BLWP @VSBW CI R4,32 JGT RV INC R0 CI R0,R13 JNE LP CLR R0 JMP CK (OR JMP EX)? RV MOV R0,R5 MOV R5,R7 LI R1,1 AI R7,1 - MOV R7,R8 | SRL R7,5 | SLA R7,5 | X S R8,R7 | ABS R7 | BL @VL - MOV R5,R7 - SRL R7,5 | Y AI R7,1 | BL @VL - CLR R7 - MOVB R6,R7 | SWPB R7 | C AI R7,>0060 | EN BL @VL MOV R10,R11 CLR @>837C STATUS B *R11 EX CLR R0 LI R1,1 CLR R7 BL @VL BL @VL JMP EN VL MOV R7,@>834A BLWP @>601C DATA >7200 BLWP @>6040 INC R1 B *R11 DF DATA >FFFF,>FFFF,>FFFF,>FFFF

Back in the day, I translated my guitar notes one by one to TI Call Sound statements, it was tedious but a joy to hear your pieces play back on the TI. One days work would easily compile 3-4 complete tunes. It is the low tech version of what you are looking for, LOL. Regards Arto.

Great work! Speccery and JasonACT it looks like I don't need to create a special side port Mini card as you guys have developed it, in front of my eyes. This card should plug into the Mini expansion system with out a hiccup. I have a Pico I was going to use for my development learning curve, I think I might reserve it for your new boards. Thanks again, looking forward for the next few chapters on the Picoart, regards Arto.

Hi All, I hope this fixes the 3.3v <> 5v issue, the LVC is the translator. Quoted "You must connect VCC to your logic level you want to convert to (say 3.3V), Ground connects to Ground. Wire OE (output enable) to ground to enable the device and DIR (direction) to VCC. Then digital logic on the A pins up to 5V will appear on the B pins shifted down to the VCC logic.". The HC AND gate can run on 3.3V Logic levels. Now I have to learn about the F18a FGPA files and the Tang 9K to test it, LOL TI99-Tango V4 1 Tang Nano 9K U1 2 74LVC245 U3,U4 1 74HC08 U6 3 4.7K R1,R5,R9 3 2.2K R2,R6,R10 3 1K R3,R7,R11 3 480 ohm R4,R8,R12 2 47 ohm R13,R14 1 4 pin Dip sw SW1 1 VGA 15 pin DSUB1 1 Schottky Diode DS1 3 1N4007 D9,D10,D11

Hi All, It looks like I have to reread the Tang PDF, the input/output might have to be 3.3v? Update coming.

Hi All, Over at Classic Computing section there is a thread about the replacement of the TMS VDP chip with a Tang 9k. I would like to thank retrocanada76 for all his good work, he has been working on a VDP replacement for the Nabu and this one hit the jackpot!! Using a Tang was a stroke of genius, here is my TI99 version 3 without surface mount. Now you can use HDMI or VGA and get V9938 graphics, Regards Arto.

Thanks for your good work retrocanada76, I have been working on a VDP replacement for a while and this one hit the jackpot!! Using a Tang was a stroke of genius, here is my version 3 without surface mount. Regards Arto

Hi All, As I have been putting these boards together, I realised that the 64/64 IO board will trigger the sound chip, so I have moved the addressing to >9300 just as Ross Mudie did back in 1988, this will only be a problem if you have the speech synth attached. Here is the updated Schematic. Regards Arto Schematic_TI99-Wire Interface V3_2023-05-16.pdf

Hi All, I tried to find the 2889-2446 chip (U26) with no luck, so I decided to look at the logic and realised it should be a Ram chip of some sort. I found a CY7C148-35PC that matches the pin outs and is a 1024x4 bit static Ram chip and with the Decoded MBE_ that is on the card using a 74LS138(U3) (DSR >4000-..) it is a I/O location when it gets access via A9-A13 (max 007F) at = >4000 + >001F = >401F to the CS_. A Nand gate also decodes >5FC0->5FFF so the Eprom gets a CS_ on pin 20. So there is code written in the DSR Eprom that is used to access routines specially written for this card. I have to hunt for for a copy of it now. From the Data Sheet: Functional Description The CY7C148 and CY7C149 are high-performance CMOS static RAMs organised as 1024 by 4 bits. Easy memory expansion is provided by an active LOW chip select (CS) input and three-state outputs. The CY7C148 remains in a low-power mode as long as the device remains unselected; i.e., (CS) is HIGH, thus reducing the average power requirements of the device. The chip select (CS) of the CY7C149 does not affect the power dissipation of the device. Writing to the device is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the I/O pins (I/O0 through I/O3) is written into the memory locations specified on the address pins (A0 through A9). Reading the device is accomplished by taking chip select (CS) LOW while write enable (WE) remains HIGH. Under these conditions, the contents of the location specified on the address pins will appear on the four data I/O pins. The I/O pins remain in a high-impedance state when chip select (CS) is HIGH or write enable (WE) is LOW. Here is the card at 95%, where it will stay until I find the DSR Eprom copy. Regards Arto.