Artoj

Thank you for the prompt reply, I find it curious that this was never explained clearly. I am looking into the GROM circuitry so I can start to write software. What I have gathered so far, is TI created a system that can run programs with a minimum of RAM and a maximum of control. The only loss was speed and a slight increase of complexity. The GPL language is an amazing journey and Speccery has unlocked a lot of it's potential. I am looking forward to applying this knowledge into programming. Thanks Ksarul for you insight, regards Arto.

Hi All, I am not sure why the 74LS139 pins 4/5/6/7 are not connected to anything and what I can figure they are for adding RAM (6264) on pin 20 (CE#). Can anyone who reads German or who has built the circuit let me know. Regards Arto.

Thank you so much, I will be going through a thorough GPL learning session soon and I will need every titbit to move forward. any suggestions on reading material to make things easier. Regards Arto.

Let us consider a 3D printed case, then try multiple finishes. A fair few printers can do the TI case size of 380x260, most can't, still you can do a seam at 255x260 + 125x260. has anyone have a TI99/4A STL file?

Hi All, I have fixed the errors and added the mechanical situation with the Male Header Pins on the socket, the fit is within +- 0.1mm accurate. Regards Arto.

Hi All, I separated the 32k SRAM so you can disable it, in case you already have it. The 2 MB (256k x 8 ) is now free to use in anyway that you can via bank switching or such. I will leave at this stage, as I need to work on the DSR for the PIO/TERNARY. Regards Arto. (I have made a few error in the diagram, I will update as soon as possible,Arto)

Hi All, I managed to fit the 2 Meg SRAM chip (including level shifter buffers - 3.3v to 5v) with the 32k as the first bank, the use of all the RAM will depend on using part of the GPIO ports (5 bits or more?). The Cartridge extension board will be revamped with sockets to fit all the leads. I will be spending a lot of time getting the SRAM banking system working transparently. The current design is only a detailed excursion and will need lots of testing to get it to fit and work without hiccups. I will release all the schematics and designs when I have passed the prototype stage. Regards Arto.

Here is the rough of the back plane, the IR control would be at the front of the console.

Here is the latest

LOL, sorry i know little about MDOS or Geneve, but still i cannot fit the 32K at present as I have added a MIDI in/out, a RS232 port and a Infrared 2 way port (as suggested by Homeautomation and his work). The prime criteria was a low profile board that does not get in the way of the GROMS and gives you a few new options for those who want connectivity. Maybe a 2MB static ram, I think there is just enough room to fit it in. Regards Arto.

As these are purely hardware mods and does not affect the operating system, I guess mdos will work fine. At present the V9958 needs no extra software as it will run in 9929/18 mode when running on a stock system, where the I2C and the GPIO will need assembly to be usable. I hope to use a myGROMY to add calls of these interfaces to TI Basic, I have yet to add 32K/MIDI/RS232 and a PIO port. I hope to make this a add-on board for any stock TI99/4A with a myGROMY chip, this should upgade the old TI99/4A without a giant PEB. Remember the I2C will give you a gateway to SD cards, USB and SPI converter chips. Regards Arto

Hi All, While going back over a few of the ideas I have being looking at, the V9958 with HDMI on the Tangnano20k is a definite goer. So I put together the I2C and a 16 bit GPIO with the Tangnano20k and make it fit inside the case, which I have called TI-TANGO. This is only a preliminary excursion to make sure it will all fit inside. A set of ribbon cables must be used to bridge parts of the circuit, H1/H2 and H5/H8 and H4 goes to the back of the Cartridge port, the only other soldering will be the sound port pin connection. The choice of a back plane is still to be decided while the addition of 32K is also another part not done as yet. The I2C uses the spare pin of the TMS9901, giving you control of the I2C port by, R12 = >0000 with TB 12, TB SBO SBZ 16, TB SBO SBZ 17, which are enough to do the job, this still needs some prototyping.(as per S Conner). You will need to reposition the TMS9901 and add a socket, while the TMS9929/18 needs to removed and a socket added as well. The GPIO uses 74ls259/74ls251 to give you 16 bits of I/O by, R12 = >0400 with CRU bits 0 to 15. (as per T Nouspikel) Regarding the Tangnano20k you will need to follow the thread on the Atari forum for more details (as per Retrocanda76). Regards Arto

Hyvää päivää, I have been looking at the console and there are 3 pins not used on the TMS9901, 38+37+29 - P0 P1 P10, where P10/INT12 is set high with a 10K resistor. These spare CRU lines could be used to implement a MIDI, I2C or SPI interface or even a RS232, so without too many hardware lines to get a simple device service routine to be incorporated into a console GROMmy. This could add so much to the bare console by adding a few new calls, such as CALL MIDI(INOUT,DATA$) or CALL I2C(INOUT,DATA) etc... maybe not even calls but just as Basic commands that can be used to manipulate data for each type of device. Regards Arto.

Greg, the plan would be to include these routines into the TI Basic console while giving you added Basic commands, such as CALL MIDI(IN,DATA) and CALL I2C(OUT, DATA) and CALL SPI(IN, DATA) etc.... So instead of a lumpy circuit with a DSR ROM and all the interface chips required to make these things to work via the buses, you can use a few spare CRU lines (P0 P1 P10) from the TMS9901 and add the GPL Device Service Routines into a modified GROMY, I will suggest this to Speccery, regards Arto.

Thanks Greg, so it is a conversion cable that uses the RS232 (TMS9902 chips) and configure it as a Midi in the software, I designed a MIDI port back in 1986 from Peter Schubert's MiniPEB RS232, which had the 'MIDI' already configured in the DSR, this is already on one of my current designs. It might be more direct to create a dedicated MIDI port and see if we can add the DSR into a GROMY chip, there are a few spare CRU lines that can easily reconfigured, if that was the case, it might be prudent to add a I2C and a SPI port as well these would make it much easier to interface a lot of current modules. Maybe a small board with ports at the back, inside the console? Regards Arto.

Hi Ray, I have been working on a couple of MIDI circuits and still haven't settled on which design would be better to use. Is your MIDI Master a PEB card or ?, regards Arto.

If you use time as a measure of productivity then you will 'Kill Time' and "Waste Time', to me time is a tool, if used wisely it helps me understand what has been and what can be. Learning from out past can only make our future better for all. technology is never "Obsolete', only the paradigm that spawned it has passed by. Are you wiser for understanding a "Subroutine" or for pressing a key, we know the former can enrich and the latter is of little consequence. I still use a primitive technology called a pencil, without it I would not have been an Artist. As a Artist/Writer I have been blessed with a creative spirit, the retro computer was one of the first creative forays into our daily lives,it did not spy on you or tell you lies, it was an obedient servant that did what the owner required, the more you understood it the more you could get from it. Today we have a monstrosity that spies and lies and you have little control over it, while it is very hard to understand its complete workings, it does offer a lot of entertainment and much more time to 'Waste'. Regards Arto.

Hi newTIboyRob and fellow TIers, After reading some of the posts regarding the inconvenience and unreliable nature of the Cassette player for storing programs and data, I decided to have a go at designing a digital tape player. I looked around and found the aPR33A3 28 pin chip was the best choice, I soon realised that it could plug directly into the back of the TI99/4A without too many issues. (this is only a prototype design) (ref pic) The 8 buttons on the left are the memory storage locations, the slider switch is for play and record and the last button is to stop all operations and go to standby. I did not include a battery as the data is not lost when the power is turned off. I have included a few extra jumpers in case you want to control the device from assembly using the CRU. SBZ 22 = record SBO 22 = play SBZ 23 = start Memory 1 SBO 23 = stop Memory 1 The resistor R3 in the PDF sets it at 47K which gives you 341 seconds (5.683 min) with a sampling frequency of 12khz. This can be changed, here is the chart: Resistance Freq Sec Min 189k 6k 682 11.36 147k 7k 584 115k 8k 512 95k 9k 454 76k 10k 408 60k 11k 372 47k 12k 341 5.683 The TI Cassette signals uses: 689.37 hz = 0 1379 hz = 1 The 3D picture shows the DB9 Port on the wrong side of the PCB. I have not completed this work as yet, I will be adding other options and further investigations in the future on my Mini PEB thread, Regards Arto

Hi All, I have updated the Ternary to Binary card to get 2 Ternary input bits and give you 4 Binary bits, so with 2 cards you will get 81 values by filling the 8 bit binary port thus giving you 1 complete 4 bit Ternary Output and a 4 bit Ternary Input port with only 1 PIO card, 1 Bin to Tern card, 2 Tern to Bin cards and the 15 pin Port card. This would be the minimum complete and useful TI99 Ternary card. Regards Arto.

Hi All, (This Document is only a DRAFT) I have a many more months of work on the house and workshop, so in the mean time I have completed the drawings for the hardware for Version 1 of the TI99/4A PARRALLIZER. I am working on the DSR at present, this will take me a few weeks/months to get it clean and functional. It should be: Capable of stacking to give you 4 complete Parallel Ports. It will be IBM compatible ECP etc. Bi-directional. The DSR will give you extra routines, listed below (plus more, let me know?) It is the first available TERNARY 8 bit parallel OUTPUT port available on any computer. The standard PIO gives you 0 to 255 bit control, this port will be -3280 to 3280, 6561 bits of control. With the ternary OUTPUT Port at my present design, you must attach a Daughter board. The second Daughter Board is a 15 PIN port for external control/input. The third to the 10nth daughter boards will give you a 1 bit INPUT for each ternary signal.(stacked) Due to the nature of interfacing Ternary I have to use 2 PIO ports to drive the complete 8 bits. Otherwise you can still use -40 to 40 for a single Binary port, giving you 81 bits of Ternary control. The arrangements are as follows: you can have 4 PIO ports You can have 2 PIO ports and 1 Ternary Port You can have 2 Ternary Ports. You can stack each Ternary Input card as you require them. Giving you: from to 1 bit 3 -1 0 1 2 9 -4 0 4 3 27 -13 0 13 4 81 -40 0 40 5 243 -121 0 121 6 729 -364 0 364 7 2187 -1093 0 1093 8 6561 -3280 0 3280 The INPUT boards can be reduced to a single board, this will be done when I have designed a cheaper version. I have already made the design using Optical Relays, but the cost is way too high. Hopefully I can reduce the footprints of all the boards in the near future. CALL LINK("PIOUT",N) N is an integer between 0 and 255 and can be an explicit number or a numeric variable. The number is converted to binary and put out on the 8 data lines of the parallel port. This will allow you to control any or all of the data lines just by selecting the appropriate number. CALL LINK("PIOIN",V) V is a numeric variable. This call will read the data lines of the parallel port, convert them to a decimal number, and place it in the variable. As the number is from 0 TO 255 you will be able to tell which data lines were active. CALL LINK("PIOSTAT",N,BININ) N is the selected status line, 0 to 7, BININ is the logic state of the line 0 or 1 0 CARD STATUS INTERNAL DSR 1 PIO DIRECTION INTERNAL DIR 2 LED STATUS INTERNAL LED 3 ERROR/SPAREIN PIN 15 4 SELECT/SPAREIN PIN 13 5 PE/SPAREIN PIN 12 6 ACK/SPAREIN PIN 10 7 BUSY PIN 11 CALL LINK("PIOCNTL",N,BINOT) N is the selected control line, 0 to 4, BINOT is the logic state of the line 0 or 1. 0 STROBE PIN 1 1 AUTOFEED PIN 14 2 INIT PIN 16 3 SELECT PR PIN 17 (ENABLE TERNARY PORT) 4 SPAREOUT (LINK) PIN 14/16/17 CALL LINK("TIOOUT",N,P) N is an integer between -3280 and 3280 and can be an explicit number or a numeric variable. The number is first converted to binary and put out on the two 8 data lines of the PIO port 1/2 or 3/4. This will allow you to control any or all of the ternary data lines just by selecting the appropriate number. P is an integer 1 to 4, it is for choosing the PIO port you use for the Ternary Output. CALL LINK("TIOIN",V,P) V is a numeric variable. This call will read the data lines of the two PIO ports, convert them to a decimal number, and place it in the variable. As the number is from -3280 TO 3280 you will be able to tell which data lines were active. P is an integer 1 to 4, it is for choosing the PIO port you use for the Ternary Input. CALL LINK("TIOEN",N,3) N is either 1 or 0, 1 will turn on the Ternary port, 0 will turn it off.(this is selectable from CRU 0 to 4, my choice CRU 3 - Select PR) CALL LINK("USERP",N,U) N is either 1 ot 0, switching on/off on the Ternary port. U is integer between 1 to 3, these are your User Control Port numbers. Here is the comparison between IBM and my TI port. IBM Bit 7 6 5 4 3 2 1 0 LPT1 LPT2 LPT3 +---+---+---+---+---+---+---+---+ DATA |DB7|DB6|DB5|DB4|DB3|DB2|DB1|DB0| Base + 0 = 278/378/3BC Hex (632 888 956) +---+---+---+---+---+---+---+---+ PINS | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | +---+---+---+---+---+---+---+---+ STATUS |BSY|ACK| PO|SEL|ERR| - | - | - | Base + 1 = 279/379/3BD Hex (633 889 957) +---+---+---+---+---+---+---+---+ PINS | 11| 10| 12| 13| 15| - | - | - | +---+---+---+---+---+---+---+---+ CONTROL | - | - | - | - | PS|INI|ALF|STB| Base + 2 = 29A/37A/3BE Hex (634 890 958) +---+---+---+---+---+---+---+---+ PINS | - | - | - | - | 17| 16| 14| 1 | +---------------+---+---+---+---+ 2nd PIO Port also Ports for Ternary interface TI99 NEW DEDICATED PIO R12 = >10x0 .-----------------------------------------------. R12 | R12 | R12 R12 | Bit 7 6 5 4 3 2 1 0 PIO1 >1000 |PIO2 >1010 | PIO3 >1020 PIO4 >1030 | +---+---+---+---+---+---+---+---+ | | | DATA |DB7|DB6|DB5|DB4|DB3|DB2|DB1|DB0| >5000 |>5002 | >5004 >5006 | +---+---+---+---+---+---+---+---+ 20480 |20482 | 20484 20486 | PINS | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | .-----------------------------------------------' +---+---+---+---+---+---+---+---+ STATUS |BSY|ACK| PO|SEL|ERR| - | - | - | CRU TB = 2 6 4 5 3 +---+---+---+---+---+---+---+---+ PINS | 11| 10| 12| 13| 15| - | - | - | +---+---+---+---+---+---+---+---+ CONTROL | - | - | - | - | PS|INI|ALF|STB| CRU SBO = 5 4 6 2 +---+---+---+---+---+---+---+---+ CRU SBZ = 5 4 6 2 PINS | - | - | - | - | 17| 16| 14| 1 | +---------------+---+---+---+---+ Regards Arto.

Thanks everyone, I have been looking at ways of creating a USB device without the specialised SMD chips. I am figuring a single function DSR and a USB 1.1 implementation is doable on a stock TI99. RickyDean's link has made my digging much simpler, I was also bamboozled by the 650 page wad, it left me cold. I will look into using old school through hole 74' type chips as well. The industry have cloaked the USB interface with corporate secrecy and not to be fiddled and hacked by the likes of the electronic hobbyist, it just makes the USB carrot more juicy. With so many bright minds here, I am sure we can crack this egg!! At present I have been preparing to write a DSR for one of my other projects, if we can work out the complete transmission procedure and map it to a set of differential serial ports, I think we can do it, regards Arto.

Hi All, Peter (Original Mini Expansion designer) came over and was very positive about all of his boards I have redesigned and revamped. I am still clearing out and rebuilding the workshop, in the meantime I have made a basic Clock that has some potential for experimenters, it uses the same >8640 address as all other clocks. I have been working on my Relay Logic Trainer, and will make it both Binary and Ternary compatible and possibly a TI99 cartridge interface for experimenters. Thanks for your patience, regards Arto.

I finally figured out the chip that should be correct, amazing enough after double checking it was just a 1024x4 TMS2114, I don't know where Peter got those numbers on the sheet, I am guessing it was a supplier part number not the manufacturers actual part number. The DSR EPROM is the greatest problem at the moment, I found a few of the old printed listing for the DSR, it looks like it has many parts, as the PIO/RS232 is a separate program segment than the Floppy DSR. I have redesigned the PIO so it matches the complete IBM PIO as shown, I added 2 more chips and the DSR must be modified as well. Regards Arto PIO - IBM standard Pin Register Direction Signal 1 Control 0 I/O Strobe 2 Data 0 I/O DB0 3 Data 1 I/O DB1 4 Data 2 I/O DB2 5 Data 3 I/O DB3 6 Data 4 I/O DB4 7 Data 5 I/O DB5 8 Data 6 I/O DB6 9 Data 7 I/O DB7 10 Status 6 IN Acknowledge 11 Status 7 IN Busy 12 Status 5 IN Paper Out/End 13 Status 4 IN Select 14 Control 1 I/O Auto Linefeed 15 Status 3 IN Error 16 Control 2 I/O Initialise 17 Control 3 I/O Select Printer 18 Ground 19 Ground 20 Ground 21 Ground 22 Ground 23 Ground 24 Ground 25 Ground

Thanks, I always need to do more reading (LOL, I read the reviews ), i have quite a lot of computer books and I think they reference Knuth, it looks like a good read, I will be getting a copy at some point. Ternary computing has been more an Art form for me rather than one of Electrical or Computer Engineering, I arrived at its implications through the study of the natural world (as an Artist) and it's hidden arithmetic (Harmony of proportions, Magic squares, Fibonacci etc) where 3 is a closer approximation to 2.718 than 2 (natural growth e, the base of natural logarithms). Regards Arto.

TI99 Mini Mega Ram V2 The first version was in 1986 in a sketch I made and how I could address a very large RAM. I have only recently revised my methodology and I will revert back to the original ideas it when this current system has been proven and it works. The final object is to address at least 4GB of RAM, by adding another 8 bits to this address bus set up. I have separated the read address and read data and the write address and data, so you can easily do copy and move functions without losing track of your address location. The great thing is you can do all this in BASIC as well. CALL LOAD(-27904,ADRESSA) A0 A1 A2 A3 A4 A5 A6 A7 CALL LOAD(-27903,ADRESSB) A8 A9 A10 A11 A1 A13 A14 A15 CALL LOAD(-27902,ADRESSC) A16 A17 A18 A19 A20 A21 A22 A23 CALL LOAD(-27901,DATAOUT) 8 BIT BYTE CALL LOAD(-27900,ADRESSA) A0 A1 A2 A3 A4 A5 A6 A7 CALL LOAD(-27899,ADRESSB) A8 A9 A10 A11 A1 A13 A14 A15 CALL LOAD(-27898,ADRESSC) A16 A17 A18 A19 A20 A21 A22 A23 CALL PEEK(-27897,DATAIN) 8 BIT BYTE The scheme here is to prove the 24 bit bus system then expand it to 32 bit addressing. The original (86) scheme used far less chips and directly addressed one large chip. This version can address 16mb of static RAM, with a possibility of adding battery backup on another version. If I added battery backup to each module, you could swap out the module as a portable memory storage. The only change would be the module and not the main board, a home made SD Ram card if you like. I made it this way so you I could design different modules from different sources, as a lot of the 2Meg static RAM chips have different pin-outs, while the prices were another consideration as well. Depending how keen you are, there is a provision to add 3 more boards to give you a total of 64 Megabytes of RAM!, you might have to beef up the power supply to do this though. These incursions into memory systems was made so I could apply ternary logic to standard static RAM. This is my final goal, once achieved, I think a Ternary CPU will be the next logical step. I will be making small Kits at some point for my different TI projects and a Ternary Relay Primer Kit is being assembled at present. Thank you for all your encouragement in these endeavours, regards Arto. MSB LSB ADDRESS 11 1111 1111 2222 0123 4567 8901 2345 6789 0123 ADRT1 >9300 ADDRESS------>0 0 0 BITS FOR DATA OUT 1111 1111 0000 0000 0000 0000 ADRT2 >9301 ----------------^ ^ 0000 0000 1111 1111 0000 0000 ADRT3 >9302 ------------------! 0000 0000 0000 0000 1111 1111 DTAUT >9303 DATA BYTE OUT 8 BITS ADRN1 >9304 ADDRESS------>0 0 0 BITS FOR DATA IN 1111 1111 0000 0000 0000 0000 ADRN2 >9305 ----------------^ ^ 0000 0000 1111 1111 0000 0000 ADRN3 >9306 ------------------! 0000 0000 0000 0000 1111 1111 DTAIN >9307 DATA BYTE IN 8 BITS ************************************************************************************************************ DATA1 >48 72 H DATA2 >45 69 E DATA3 >4C 76 L DATA5 >4C 79 O READB BSS 32 FILLING ADDRESS >0FF000 TO >0FF004 WITH "HELLO" 0000 1111 1111 0000 0000 0000 BANK RAM 1 AS A WORD MOVE LI R0,>0FF0 SET MSB LI R1,>0048 SET LSB + BYTE "H" LI R2,>0145 SET LSB + BYTE "E" LI R3,>024C LI R4,>034C LI R5,>044F MOV R0,@ADRT1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO WRITE (WORD) MOV R1,@ADRT3 LOAD LSB + DATA TO SEND ADDRESS TO LATCHES THEN WRITE DATA TO RAM (WORD) MOV R0,@ADRT1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO WRITE (WORD) MOV R2,@ADRT3 LOAD MSB + DATA TO SEND ADDRESS TO LATCHES THEN WRITE DATA TO RAM (WORD) MOV R0,@ADRT1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO WRITE (WORD) MOV R3,@ADRT3 LOAD LSB + DATA TO SEND ADDRESS TO LATCHES THEN WRITE DATA TO RAM (WORD) MOV R0,@ADRT1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO WRITE (WORD) MOV R4,@ADRT3 LOAD LSB + DATA TO SEND ADDRESS TO LATCHES THEN WRITE DATA TO RAM (WORD) MOV R0,@ADRT1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO WRITE (WORD) MOV R5,@ADRT3 LOAD LSB + DATA TO SEND ADDRESS TO LATCHES THEN WRITE DATA TO RAM (WORD) READING BACK FROM THE SAME ADDRESS LI R0,>0FF0 SET MSB LI R1,>0000 SET LSB + CLEAR DATA BYTE LI R2,>0100 SET LSB + CLEAR DATA BYTE LI R3,>0200 SET LSB + CLEAR DATA BYTE LI R4,>0400 SET LSB + CLEAR DATA BYTE LI R5,>0500 SET LSB + CLEAR DATA BYTE MOV R0,@ADRN1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO READ (WORD) MOVB R1,@ADRN3 LOAD LSB TO SEND ADDRESS TO LATCHES READY TO READ (BYTE) MOVB @DTAIN,@READB READ BYTE (BYTE) MOV R0,@ADRN1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO READ MOVB R2,@ADRN3 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO READ MOVB @DTAIN,@READB+1 READ BYTE MOV R0,@ADRN1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO READ MOVB R3,@ADRN3 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO READ MOVB @DTAIN,@READB+2 READ BYTE MOV R0,@ADRN1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO READ MOVB R4,@ADRN3 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO READ MOVB @DTAIN,@READB+3 READ BYTE MOV R0,@ADRN1 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO READ MOVB R5,@ADRN3 LOAD MSB TO SEND ADDRESS TO LATCHES READY TO READ MOVB @DTAIN,@READB+4 READ BYTE