JonnyBritish Posted May 21, 2011 Share Posted May 21, 2011 On the TI99/4a is it possible to turn of the screen update before writing a bunch of characters then turn it on again? Quote Link to comment Share on other sites More sharing options...
sometimes99er Posted May 21, 2011 Share Posted May 21, 2011 (edited) Yes, VDP write-only register 1. The default for register 1 is >EO in the Editor/Assembler, TI BASIC, and TI Extended BASIC. Before changing this register, put a copy of the new value you wish it to have at address >83D4. When a key is pressed, a copy of the value at this address is placed in register 1. Bit 1 is blank enable/disable. A value of 0 causes the active display (the entire screen) to be blank, and a value of 1 allows display on the screen. With a value of 0, the screen only shows the border color. ref.: E/A-manual page 326. Edited May 21, 2011 by sometimes99er Quote Link to comment Share on other sites More sharing options...
matthew180 Posted May 23, 2011 Share Posted May 23, 2011 The OP did not mention what environment they are using. If XB, then an assembly "helper" program would be needed. It would not be to big of a deal to write one. Does anyone know if such a routine already exists for XB? Quote Link to comment Share on other sites More sharing options...
+OLD CS1 Posted May 24, 2011 Share Posted May 24, 2011 Is there any performance gain by turning off the screen? I have seen on other systems where, when doing so, the video processor does not have to fetch data from RAM thus giving a slight increase in speed. Of course, with the wait-states injected into the system, turning off the screen may be moot. Quote Link to comment Share on other sites More sharing options...
Tursi Posted May 24, 2011 Share Posted May 24, 2011 Is there any performance gain by turning off the screen? I have seen on other systems where, when doing so, the video processor does not have to fetch data from RAM thus giving a slight increase in speed. Of course, with the wait-states injected into the system, turning off the screen may be moot. Nope, the CPU does not share a bus with the VDP RAM, so there's no intrinsic performance gain. However, while the screen is blanked, all VDP cycles are RAM access cycles, which means you do not need delays between reads/writes to VRAM. (However, on a stock 99/4A it's rather difficult to overrun the VDP anyway, there are only a couple of cases where it's possible). Quote Link to comment Share on other sites More sharing options...
+OLD CS1 Posted May 28, 2011 Share Posted May 28, 2011 Nope, the CPU does not share a bus with the VDP RAM, so there's no intrinsic performance gain. However, while the screen is blanked, all VDP cycles are RAM access cycles, which means you do not need delays between reads/writes to VRAM. (However, on a stock 99/4A it's rather difficult to overrun the VDP anyway, there are only a couple of cases where it's possible). Yes, I should have known that. Thanks Quote Link to comment Share on other sites More sharing options...
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