Pokey decap

[ijor]

Pokey reconstructed schematics in searchable PDF format:

 

PokeyReSchem-13.pdf

(Latest version with a couple of corrections)

 

Thanks to the Greg James ( from Visual 6502) for decap and taking the die shoots, and to Ivo for donating the chip. See the first page for notes and comments.

 

I'd recommend using this together with the original schematics, and the excellent work by Perry and Piotr done at Pokeydocs (should be somewhere here in this forum, just note one wrong cell on each channel counter).

 

Older versions:PokeyReSchem.pdf PokeyReSchem-12.pdf

 

 

Edited March 6, 2023 by ijor
Posted updated schematics

[Rybags]

Cool.

 

I noticed the other day there's a die photo of GTIA floating around - has anyone done any work with that yet?

[ijor]

I noticed the other day there's a die photo of GTIA floating around - has anyone done any work with that yet?

 

Greg (again, from Visual 6502) posted the GTIA die shoots just about two weeks ago . He is supposed to decap and photograph CTIA anytime soon. This time both chips were donated by Bryan.

Edited May 31, 2011 by ijor

[R4ngerM4n]

[Bryan]

I noticed the other day there's a die photo of GTIA floating around - has anyone done any work with that yet?

 

Greg (again, from Visual 6502) posted the GTIA die shoots just about two weeks ago . He is supposed to decap and photograph CTIA anytime soon. This time both chips were donated by Bryan.

 

GTIA appears to contain the following initials: JN DH. What happened to George McLeod?

[atx4us]

Pokey reconstructed schematics in searchable PDF format:

 

PokeyReSchem.pdf

 

Thanks to the Greg James ( from Visual 6502) for decap and taking the die shoots, and to Ivo for donating the chip. See the first page for notes and comments.

 

I'd recommend using this together with the (unreadable) original schematics, and the excellent work by Perry and Piotr done at Pokeydocs (should be somewhere here in this forum, just note one wrong cell on each channel counter).

 

I was also hoping to see picture(s) of the die with the key areas labeled. Any chance you can share that with us?

[ijor]

I was also hoping to see picture(s) of the die with the key areas labeled. Any chance you can share that with us?

 

Do you mean a floorplan, as I posted for Antic? I don't currently have a floorplan already drawn, but I can draw one and post it.

 

Note that it probably won't be as interesting as you might think. The floorplan is designed around a datapath, as it is more common in CPUs.

[atx4us]

I was also hoping to see picture(s) of the die with the key areas labeled. Any chance you can share that with us?

 

Do you mean a floorplan, as I posted for Antic? I don't currently have a floorplan already drawn, but I can draw one and post it.

 

Note that it probably won't be as interesting as you might think. The floorplan is designed around a datapath, as it is more common in CPUs.

 

Yes, the floorplan would be interesting to see, IMHO. If you already posted it in Antic, can you just give us the reference or a link to it?

[ijor]

Here is the Pokey floorplan:

 

 

Note again, the heavy datapath construction (as opposed to ANTIC). All the registers ( and their associated logic), that can be read or written by the CPU, are in those high columns. Those columns are traversed by the 8-bit data bus. Lower bits are at the bottom.

 

Also note the huge space taken by all the eight POTs logic.

 

atx4us: The ANTIC floorplan is in this thread: http://www.atariage.com/forums/topic/172580-antic-decap-and-reverse-engineering

Edited June 1, 2011 by ijor

[atx4us]

Here is the Pokey floorplan:

 

 

Note again, the heavy datapath construction (as opposed to ANTIC). All the registers ( and their associated logic), that can be read or written by the CPU, are in those high columns. Those columns are traversed by the 8-bit data bus. Lower bits are at the bottom.

 

Also note the huge space taken by all the eight POTs logic.

 

atx4us: The ANTIC floorplan is in this thread: http://www.atariage.com/forums/topic/172580-antic-decap-and-reverse-engineering

 

Ahh, ANTIC! I got it! Thanks for the postings. These are really cool!

[Keatah]

Maybe we could let loose a bunch of nanites and have a party in pokey!

[fox]

Excellent job! Thanks a lot! When can we expect GTIA?

 

Excuse my ignorance, but could you please explain these symbols:

[Creature XL]

Excellent job! Thanks a lot! When can we expect GTIA?

 

Excuse my ignorance, but could you please explain these symbols:

 

<deleted>

 

EDIT:

Damit I should have looked first

 

Seems to be a NOR.

 

http://www.tpub.com/content/firetrucksandequipment/TM-9-254/img/TM-9-254_228_1.jpg

 

And the trianlge is a NOT-gate

Edited July 31, 2011 by Creature XL

[ijor]

Hi fox,

 

When can we expect GTIA?

 

Shortly I am working on it.

 

 

Excuse my ignorance, but could you please explain these symbols...

 

The symbol on the right is a clocked NOR with one async input. I used here the same schematics style as in the original Pokey schematics (quite different than GTIA and TIA ones), and the meaning of these clocked gates is explained at the last page of those schematics. A gate with a number 1 or 2 inside, means that the gate is clocked with the corresponding phase of the clock. This is realized with clock couplers, controlled by the named clock phase, at the input of the gate. An input marked with an X in turn means that the particular input is not clocked. In other words, there is no clock couper (pass transistors) and that specific input is connected directly to the gate.

 

Another way to look at this is as follows. This is a NOR, changes to the bottom async input apply immediatately. Changes to the top (synchronous) input are deferred during the phase 2 of the clock.

 

The other gates are Super Buffers. This is a circuit that modifies the analog characteristics of the gate, power and timing. You can ignore the alternate path, because it doesn't affect digital functionality. The alternate path is whatever ends in the middle of another gate (instead of ending as the input of another game).

 

The one at the left is a regular, non-inverting Super Buffer. If you ignore the alternate path at the top, you get just two inverters in a row, or a simple buffer.

 

The one at the middle is a Super Inverter, or an inverting Super Buffer. If you ignore, again, the alternate path at the top, you get a simple inverter.

[ijor]

Errata

 

...(instead of ending as the input of another game).

 

I meant, of course:

(instead of ending at the input of another gate)

 

It would be nice if a moderator would correct the original post (or would let me).

[phaeron]

Apologies for reviving this old thread, but I have a timing puzzle in POKEY that I haven't been able to figure out and it's easier to relate to labels in this schematic.

 

I've been trying to come up with a cycle timing model for POKEY's timers to try to explain some odd behavior with two-tone mode, and haven't quite been able to reconcile timing tests on the hardware with the gate timing in this schematic. The behavior seen on the Atari is as follows, given a write to STIMER on cycle 0 (the last cycle of an STA instruction), and timer 1 in 1.79MHz mode:

• Last cycle to write to AUDF1 to affect the first timer 1 fire time is on cycle 2+AUDF1.
• Last cycle to write to STIMER again in time to preempt timer 1 firing is cycle 3+AUDF1.
• Assuming neither of the above two apply, timer 1 IRQ (IRQST bit 0) is asserted starting on cycle 8+AUDF1.

Hand-simulating the logic in the schematic with AUDF1=0 (these are results from each clock phase):

• Cycle 0 / phase 1: STIMER flip-flop set from address decoding.
• Cycle 1 / phase 2: reload12 = 1.
• Cycle 2 / phase 1: Ld = 1 on timer 1.
• Cycle 2 / phase 2: reload12 = 0.
• Cycle 3 / phase 1: Ld = 0, counter begins counting.
• Cycle 4 / phase 1: Bit cells 0-3 BOR=1.
• Cycle 5 / phase 1: Bit cells 4-7 BOR=1.
• Cycle 5 / phase 2: First underflow gate flips.
• Cycle 6 / phase 1: Timer1 = 1 signal goes to IRQ and audio circuitry output and timer 1 counter begins reloading.
• Cycle 6 / phase 2: First IRQ gate flips.
• Cycle 7 / phase 1: Second IRQ gate flips.

With this sequence, the timer period is correct (4 cycles) and the reload timing is correct, as a value written to AUDF1 in cycle 2 should just barely flow through to the counter being reloaded. But the IRQ timing is one cycle earlier than it should be, and STIMER preemption also seems off as by this sequence a write on cycle 4 would work. I haven't been able to figure out where the missing cycle belongs without throwing something else off like the period of the timer.

 

Any ideas?

 

[ijor]

On 9/7/2021 at 5:54 AM, phaeron said:

Apologies for reviving this old thread, but I have a timing puzzle in POKEY that I haven't been able to figure out and it's easier to relate to labels in this schematic.

 

Hi Phaeron,

 

I'm currently on a trip. I won't be able to look into this until next weekend, in ten days or so. Please bear with me, sorry.

[Mclaneinc]

Avery asking for help...

 

Oh no's, the Force is weak in him..Quick, find Yoda for some training!

[ijor]

On 9/7/2021 at 5:54 AM, phaeron said:

The behavior seen on the Atari is as follows, given a write to STIMER on cycle 0 (the last cycle of an STA instruction), and timer 1 in 1.79MHz mode:

• Cycle 0 / phase 1: STIMER flip-flop set from address decoding.

 

I'll look at this in more detail shortly, and I will also post a waveform simulation. But, if I understand correctly what you are saying, note that there is a cycle delay missing here. STIMER RS-latch is set one cycle later. The address decoder (Addr9w signal, in this particular case) is asserted at the next cycle after the CPU write cycle.

Edited September 19, 2021 by ijor

[ijor]

Pokey internal simulation waveform that shows the relation between STIMER, the audio logic and IRQ output.

 

Timer 1 is configured as 8-bit, pure tone, divisor zero and clocked by the 1.79 MHz clock.

 

Most signals use the same name as in the schematics published in this thread.

cycleCtr is a virtual cycle counter that doesn't exist at the hardware

ChannOut1 signal is the digital output of channel 1. It is the input to the channe'sl DAC.

 

The first cursor is right after the CPU write cycle to STIMER. The second cursor at the right marks the active edge of the external IRQ signal.

Let me know if you would like to see other signals included, or if you need a different simulation.

 

[phaeron]

Necrobumping again for an erratum, the middle tap for the 5-bit polynomial should be at x^3 instead of x^2:

 

[Vyvyan B.]

I'm out of my realm here a bit, I'm a network guy, not an EE, but aren't we at the point where some of these old parts could be substituted with FPGAs?

[+DrVenkman]

14 minutes ago, Vyvyan B. said:

I'm out of my realm here a bit, I'm a network guy, not an EE, but aren't we at the point where some of these old parts could be substituted with FPGAs?

Some of then have been, to varying degrees of success and accuracy. 

[Vyvyan B.]

23 minutes ago, DrVenkman said:

Some of then have been, to varying degrees of success and accuracy. 

You'd think that by now you'd be able to stick one of these old chips into a reader, analyze it with some AI and crank out a replacement FPGA in no time flat.

[+DrVenkman]

20 minutes ago, Vyvyan B. said:

You'd think that by now you'd be able to stick one of these old chips into a reader, analyze it with some AI and crank out a replacement FPGA in no time flat.

Nope. There’s no such thing as a “reader” that can analyze, identify and properly map out the functions of each internal component of an unknown IC, let alone figure out how to duplicate it such that everything works exactly the same as an original. That’s why FPGA replacements of chips isn’t perfect. In POKEY’s case, there are several different FPGA (POKEYmax,  PokeyONE …) replacements for audio, along with at least one new microcontroller replacement (Batari’s HOKEY). But in some applications, POKEY also provides paddle inputs, keyboard interface, serial I/O, and a pseudo-random number generator. Getting every bit of that working identically to vintage hardware is more of a challenge than “just” sound (which is complicated enough).