sage Posted March 30, 2013 Share Posted March 30, 2013 After a bit of bugging around: It looks like the combination prescale 0/backup 0 is behaving completly strange. a) It will never work with LINKING (channel 0-3 links to 1-4). b) It will not produce sound with some (many?) waveforms prescale 0-2 with backup 0-2 have strange behaviour with some waveforms. even if you change the timer/backup, the audible frequency does not change (but, the linked timer does!). My educated guess: with 1us reload 0 we have 1MHz clocking. Might be the chip is not able to perform the linking anymore. beeing close to 1MHz with the other prescale/realod combinations, it might be that the polycounters do not work as expected. For example, a simple len 2 polycounter (on-off) will just deliver _no_ output signal. There seems to be a difference here in integrate and square mode!? -> Timing issues??? If this is the case, can we emulate this? Most likely not. Anyway, I you like to check out a few things yourself, you are welcome. Maybe then we find out whats going on. Quote Link to comment Share on other sites More sharing options...
candle Posted March 31, 2013 Share Posted March 31, 2013 i'm not the expert here but looking at schematics and from what you wrote if polycounter lenght is 2 (single xor gate) and input clock is 1mhz, then you would have 500khz on the output - far beyond bats hearing, not to mention humans, plus there is simple low-pass filter just after pcm "audio buffers" best would be to capture digital output of pcm pins with various settings and then make a guess on how it works analog part will be easy part, and emulation will be much more accurate Quote Link to comment Share on other sites More sharing options...
sage Posted March 31, 2013 Author Share Posted March 31, 2013 i'm not the expert here but looking at schematics and from what you wrote if polycounter lenght is 2 (single xor gate) and input clock is 1mhz, then you would have 500khz on the output - far beyond bats hearing, not to mention humans, plus there is simple low-pass filter just after pcm "audio buffers" Yes, as you can see here: http://atariage.com/forums/topic/210601-frequency-response/ 500kHz is not an issue with a 40GHz oszilloscope, the problem is more that the signal is drowned in noise. And it doesnt matter if you have a a len two or length 4095 waveform, as the signal change is still at 1MHz. Picking the signal before the output circuit might improve the signal/noise ratio, yes indeed. But I am too lazy to slaughter my Lynx (again) just to acess the MB. PS: Do you have the schematics for a Lynx II? best would be to capture digital output of pcm pins with various settings and then make a guess on how it works analog part will be easy part, and emulation will be much more accurate You an monitor the polycounters very nicely with 1Hz clock rate. The question is: why do they not work for ultra high frequencies (used for hihat for example) and have the strange behaviour that soem waveforms are not processed anymore at all (like the length two). So I do not understand what you mean by "make a guess on how it works"... this is quiet obvious. Quote Link to comment Share on other sites More sharing options...
candle Posted March 31, 2013 Share Posted March 31, 2013 well, as i wrote - i'm not the expert here from what i see there is just 2 bit digital output going out from mikey chip, then analog part follows regardless of the scope used, i would just put my probes on these two pins and capture the output hihat can be just direct output from polycounter + some kind of envelope generator, but i don't want to speculate i did several sound processor designs, so i have general idea on how to do various things with sound, but my knowledge about the lynx is marginal Quote Link to comment Share on other sites More sharing options...
sage Posted March 31, 2013 Author Share Posted March 31, 2013 yes. yes. no. seems so. Quote Link to comment Share on other sites More sharing options...
sage Posted March 31, 2013 Author Share Posted March 31, 2013 The main question is, does the 1MHz Frequency prevent the poycounters from working correctly? As it is clear, not all are working, which indicate soem glitches. even if i measure the waveforms for hundereds of waveform, i guess you cannot reverse engeneer it. Quote Link to comment Share on other sites More sharing options...
candle Posted April 1, 2013 Share Posted April 1, 2013 there is no such thing that man cannot reverse engineer, since another man already made it years ago chip decap would be apriopriate but for a starters, anything would help, including original documentation - i'm sure there is someone out there who has it really makes me wonder why so far there is so little available from original documentation and yet, you have two emulators and quite big library of dev docs - i'm impressed, really am Quote Link to comment Share on other sites More sharing options...
candle Posted April 1, 2013 Share Posted April 1, 2013 erm how many 16mhz cycles mikey state machine needs to serve a channel? Quote Link to comment Share on other sites More sharing options...
TailChao Posted April 2, 2013 Share Posted April 2, 2013 erm how many 16mhz cycles mikey state machine needs to serve a channel? It should just be one. The eight timers and four audio channels all cycle through sequentially with four dead slots Quote Link to comment Share on other sites More sharing options...
sage Posted April 2, 2013 Author Share Posted April 2, 2013 It should just be one. The eight timers and four audio channels all cycle through sequentially with four dead slots thats interessting. Quote Link to comment Share on other sites More sharing options...
candle Posted April 2, 2013 Share Posted April 2, 2013 (edited) i doub't it takes one cycle it is said in hardware and sound specs for the lynx (from aage archives) that circuit process channels in sequence, more to it there are two gropu of timers group a: timer 0, timer 2, timer 4 gropu b: remaining ones, including audio timers and bit "previous" can link gp timer to audio timer meaning that state machine that updates them does them all each timer needs to load, increment and compare and then store the result, this is 3 cycles @16mhz at least resulting in 24cycles for all channels thus, no challels is updated more often than 24 cycles @16mhz, and this is too much to 1us clock setting what i don't know is whether there is 4 or 1 LFSR, this part is pretty cheap in hardware, even multitap as it is in mikey, but if they went for area, they could implement this in form of state machine too Edited April 2, 2013 by candle Quote Link to comment Share on other sites More sharing options...
sage Posted April 2, 2013 Author Share Posted April 2, 2013 i doub't it takes one cycle and bit "previous" can link gp timer to audio timer meaning that state machine that updates them does them all each timer needs to load, increment and compare and then store the result, this is 3 cycles @16mhz at least resulting in 24cycles for all channels taht depends on how this is done in hardware and in which technology. without knowiing f.e. the verilog files you cannot judge. Quote Link to comment Share on other sites More sharing options...
candle Posted April 2, 2013 Share Posted April 2, 2013 don't know your basis, so.. have you any experience in verilog or vhdl? Quote Link to comment Share on other sites More sharing options...
TailChao Posted April 2, 2013 Share Posted April 2, 2013 i doub't it takes one cycle it is said in hardware and sound specs for the lynx (from aage archives) that circuit process channels in sequence, more to it there are two gropu of timers group a: timer 0, timer 2, timer 4 gropu b: remaining ones, including audio timers and bit "previous" can link gp timer to audio timer meaning that state machine that updates them does them all each timer needs to load, increment and compare and then store the result, this is 3 cycles @16mhz at least resulting in 24cycles for all channels thus, no challels is updated more often than 24 cycles @16mhz, and this is too much to 1us clock setting Ah, I forgot about the split groups. But the timers themselves can "tick" at 1uS. Maybe it's the backup of zero that causes issues? But I'll need to check, it's just another guess. Quote Link to comment Share on other sites More sharing options...
sage Posted April 2, 2013 Author Share Posted April 2, 2013 (edited) yes (vhdl) Edited April 2, 2013 by sage Quote Link to comment Share on other sites More sharing options...
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