+mizapf Posted April 14, 2013 Share Posted April 14, 2013 Doing some "forbidden things" here ... I was curious to see what effect this has on the produced tagged object code. So this gives us some more tags, which TI should have told us about if they really meant it seriously with that "appropriate loader". Concretely, I'm about to add a disassembler for D/F 80 files to TIImageTool, so for the sake of completeness I'd like to find out about the additional tags we never heard of. The appropriate loader was something we never got to see, right? We did a lot of things in the past 30 years, but nothing here. Or did I miss something? As far as I can see, as with many other platforms, the assembler allows for defining a data area in the program as well as a text area (called program area here). Third, we can have a common segment. Obviously there should be three independent location counters in the loader; the standard loader only knows a single one, beside the absolute address counter. Watch how the assembler marks the different relocation classes. (I'm adding this as a text file since I could not get bbcode to keep the spaces and not play with tabs.) dseg.txt 1 Quote Link to comment Share on other sites More sharing options...
+mizapf Posted April 15, 2013 Author Share Posted April 15, 2013 So to clarify why I posted this (apart from the possibility that some of you always wanted to know what PSEG / DSEG / CSEG is but never dared to ask or try), my question: Does anybody have a full description of the TMS9900 tagged object code? The information from the Editor/Assembler manual unfortunately leaves out most information that is not applicable for the built-in loader. Quote Link to comment Share on other sites More sharing options...
Stuart Posted April 15, 2013 Share Posted April 15, 2013 (edited) Does anybody have a full description of the TMS9900 tagged object code? The information from the Editor/Assembler manual unfortunately leaves out most information that is not applicable for the built-in loader. There's a complete list of the tags in this document <http://bitsavers.tra..._usersGuide.pdf>, starting on page 149. But I see it doesn't include some of the tags you seem to be getting ... Stuart. Edited April 15, 2013 by Stuart Quote Link to comment Share on other sites More sharing options...
+Lee Stewart Posted April 15, 2013 Share Posted April 15, 2013 So to clarify why I posted this (apart from the possibility that some of you always wanted to know what PSEG / DSEG / CSEG is but never dared to ask or try), my question: Does anybody have a full description of the TMS9900 tagged object code? The information from the Editor/Assembler manual unfortunately leaves out most information that is not applicable for the built-in loader. Maybe not a full description, but Thierry says quite a lot under "Programming Tricks" on his E/A page here. ...lee Quote Link to comment Share on other sites More sharing options...
+mizapf Posted April 15, 2013 Author Share Posted April 15, 2013 Thanks Stuart, I just had a look, but they do not show all tags either. There are some exotic ones which I was able to tickle out of the assembler, so the list, as far as I found them in the test, would be 0x01 / byte[8] = Identifier, compressed object code 0 / byte[8] = Identifier (all following int16, byte represented as hex strings) 1 / int16 = Program entry ("END XXX"), absolute address 2 / int16 = Program entry, relocatable address 3 / int16 byte[6] = REF (relocatable address, symbol) 4 / int16 byte[6] = REF (absolute address, symbol) 5 / int16 byte[6] = DEF (relocatable address, symbol) 6 / int16 byte[6] = DEF (absolute address, symbol) 7 / int16 = Checksum (value) 8 / int16 = Checksum (value, ignored) 9 / int16 = Absolute location (location counter, from AORG) A / int16 = Program-relocatable location (location counter, RORG, default) B / int16 = Absolute contents C / int16 = Program-relocatable contents (usually a reloc. address pointer) D / int16 = Load bias (address where to start loading, not supported) F / null = end of record I / byte[8]? = Segment identifier (ignored; according to E/A manual; how to create?) M / int16 byte[6] int16 = Segment declaration (length in bytes, $DATA for DSEG and $BLANK for CSEG, id?) N / int16 int16 = Common-relocatable data (location counter, id?) P / int16 int 16 = Common segment definition (location counter, id?; created by CSEG) S / int16 = Data segment definition (location counter, created by DSEG) T / int16 = Data-relocatable data (location counter) U / int16 byte[6] = Load symbol (?, created by LOAD) V / int16 byte[6] = Secondary reference (?, created by SREF) : / null = End of file The segments seem to show that they planned to be able to build some Harvard architecture computers with the TMS9900. With the standard Von Neumann style (and no special memory handling) there was no need to include them in the loader. Quote Link to comment Share on other sites More sharing options...
+mizapf Posted April 15, 2013 Author Share Posted April 15, 2013 Yes, Thierry ... I should really keep a bookmark of his pages, and right at the start of the list. He seems to have invested quite some research already, so this seems to be the answer to many of these questions. Quote Link to comment Share on other sites More sharing options...
Stuart Posted April 15, 2013 Share Posted April 15, 2013 (edited) The segments seem to show that they planned to be able to build some Harvard architecture computers with the TMS9900. The third generation TMS99000 series processors could be operated like this. The processor has three 'bus status' pins which indicate what's going on on the bus for each cycle - getting instruction, getting operand, and so on. So by decoding these with the memory access signals, you can direct memory accesses to separate instruction and data memory banks. This technique, plus a 17th address bit, lets the processor access 256 kbyte of memory. Stuart. Edited April 15, 2013 by Stuart Quote Link to comment Share on other sites More sharing options...
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