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The only time I see the title screen is when I manage to "bungle" the ROS. Then I stuff an EA cart in the cartridge slot and press CTRL/FCTN to bypass the auto-boot and go directly to the title screen, load CFG and re-install ROS. The actual contents of the drives are almost never corrupted.

 

I'm using a custom GROM0 that "The Great Gazoo" put together for me years ago to accommodate my AVPC and HSGPLcard  

Edited by atrax27407
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Question:  why does CFG load at >E000 versus a more common address like >A000?   Anyone know?

 

Took me a while to figure out that CFG was storing data after the end of the CFG program. There was no associated BSS/EQU - nor any comment - this was the case. Certainly bad practice, bad form.  Anyway, with only two bytes free, all the data was being copied into ROM (thanks to address wraparound) and thus the recall and subsequent powerups caused a lockup.  I fixed the problem by removing the AORG >E000, did a cursory review of memory usage below >E000, and so far so good.  Hoping to make some updates to CFG this weekend. First on my list: assess and implement allowing the user to retain the defined CALLs, colors, etc. when (re)loading ROS.  I really hate entering that every...single...time. And if there is room, I'll allow that to be saved into an options file separate from ROS.

 

image.thumb.png.96a95290c1f8eaf9ce5fbccbd37154ed.png

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A few more updates.

1. ROS - Moved special CALL routines from 6k segment to 2k segment, freeing up enough space to incorporate all of the allocation bug fixes.

2. CFG - Added warning to the format/delete routine. Changed format keypress to "F" and now prompt for confirmation.  Formatting a drive removed all subsequent drives!  If you accidentally formatted the first drive, every disk was wiped out. Not cool!

3. CFG - Investigating how to add a 'reset' selection to clear/reset an existing drive using its current space allocation. Similar to a quick disk format.

4. CFG - After further review, saving CALLs and colors requires more work than I have time to commit. I have noted it as a future, possible feature.

5. ROS/CFG - The ROS startup code only displays the ROS version/date when there is no menu and no cartridge. It is seeming more like a novelty; I am again leaning toward removing it completely.

6. I uploaded some code to GitHub via their web interface but got lost trying to understand how to leverage the tool.   ?  I'll come back to that another day.

 

I need to work through a few tests tomorrow and if all goes well, I'll share the next iterations for testing purposes.

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40 minutes ago, InsaneMultitasker said:

A few more updates.

6. I uploaded some code to GitHub via their web interface but got lost trying to understand how to leverage the tool.   ?  I'll come back to that another day.

 

I need to work through a few tests tomorrow and if all goes well, I'll share the next iterations for testing purposes.

 

Tim, let me know if you need help with getting stuff to GitHub.

 

Do you do your source code editing on the TI-99/4a or Geneve or are you using a PC?

(When using a PC with Microsoft Visual Studio Code you can for example push all your code changes to GitHub with no effort. I'm doing that with my TiVi assembler source code. I have a private repo on GitHub, when I'm done changing source code in Visual Studio Code it's pushed to GitHub for offsite backup purpose).

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9 hours ago, retroclouds said:

 

Tim, let me know if you need help with getting stuff to GitHub.

 

Do you do your source code editing on the TI-99/4a or Geneve or are you using a PC?

(When using a PC with Microsoft Visual Studio Code you can for example push all your code changes to GitHub with no effort. I'm doing that with my TiVi assembler source code. I have a private repo on GitHub, when I'm done changing source code in Visual Studio Code it's pushed to GitHub for offsite backup purpose).

Thank you.   For this 'project' I am editing on the PC with Notepad, assembling/linking with XDT99, and testing on the real hardware via TIPI.  I have never used Visual Studio but it seems that what you describe re: pushing the source, etc. is what I'm trying to figure out :)  as a first step.  For most of my Geneve work I do that on the real hardware but would still copy to PC via HDX or TIPI or via TI Image Tool.

TEST RELEASE v8.42 (Post #1 updated)

I ran out of time for testing today and the week ahead is looking quite busy.  The attached ZIP contains ROS 8.42a and CFG 8.42.  The embedded ROS CRC is /not/ activated in this test version.

 

1. CFG now loads at >C000 versus >A000.  (If RAMBO is present, the page detection routine overwrites B400-B800, smack dab in the middle of CFG. Moved start address to accommodate).

2. All allocation fixes have been implemented. I haven't had sufficient time to test them thoroughly together in the same release; they all worked separately.  

3. All completed updates/fixes described during the past few weeks are present in this test release.

4. ROS is now padded at assembly time to 8192 bytes as a workaround to the TI Controller DSR LOAD opcode bug.

 

If you are concerned about your current RAMdisk contents be sure you have the files elsewhere.  If you run into problems report them here. I'll want to know the size of each drive and what operation(s) you were performing. 

 

Remember, this is a test release intended to find potential release problems and/or oversights.  

 

ROS CFG 842-TEST.zip

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2 hours ago, atrax27407 said:

FYI, I have not been able to break or corrupt CFG/ROS842. It works fine. ?

Now you've done it... famous last words!  :)   It seems to be working ok here as well.  I've even done some copying between RAMDISK and TIPI (DSK4) using Fred's DM2K without any issue.   Try some of the various CALLs if you have time and the LD (load direct) routine, e.g., DELETE "LD.5.DM2K" to load dm2k from ramdisk 5. 

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The only thing I can think of that would cause problems would be a voltage spike which would probably only take out the ROS - which could be easily reloaded.

However, (sigh) you have inadvertently created a "monster". Over the years, my 3 MEG HRD16 has grown in a fairly inconsistent and haphazard manner. The result is that I have a series of drive partitions that range in size from 720 sectors to 2400 sectors. Now, I have the distinct urge to populate it with a series of 3200 sector partitions. That means that I am going to have to re-organize all of the programs and completely re-vamp all  (or most) of my menus and access pathways. That is probably long past due since there are programs on my HRD16 that I never use (and probably never will) on a regular basis. I intend to eliminate them  and re-organize everything in a more logical manner. All I need is a long. snowy weekend   ( and a copious supply of coffee). "Fie on you O Insane One" ?

Edited by atrax27407
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I just did some preliminary testing. It seems that the absolute limit IS 127 files per partition (at least with DISK UTILITIES). Above 127 files, you get an obnoxious "Disk Directory Full" message. I surmise that the result would be the same with DISKREVIEW et. al. So, unless you have a number of large files, a 3200 sector disk partition is a semi-moot point - the utility is greatly diminished. I guess, for the present, I will keep my current configuration.

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Although the project of converting my HRD16 to a series of 3200 sector drives has been "scuttled" by the number of files per disk partition limit, I still maintain a couple of large capacity (2400+ sector drives) on my HRD16 to serve as "workspace". It is convenient to have a space to store (at least temporarily) a series of large files. This system comes in quite handy for archiving and transferring files between my TI and PC.

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The Geneve can realize more utility with the RAMDisk. Why? The OS can manage three subdirectories via a floppy format and with the not-yet-released Os, the ramdisk can be formatted with a hard drive structure. 

 

Creating a new TI DSR for the ramdisk - to leverage the hard drive structure - would be quite a mean challenge.

8 hours ago, GDMike said:

Ok. .here's my question..when will the drives come out? 

Right now, four fully-populated cards exist. All are in the hands of testers (the last one will be enroute tomorrow). I plan on ordering the finalized boards in a week, as anything that goes out now will hit the board house during their local new year vacation. In between, I may finish assembling the rest of my test boards, as the number of required modifications is not huge. I'll also need to dump about $2,000 for the required memory chips, as my stock of those is relatively limited at the moment. I have enough 128K chips on hand to build about six more 2M boards and enough 512K chips to build three more of the 8M boards. As I said, limited on-hand chip stocks.

 

I expect that the final boards will be ready to sell by the end or March or early April.

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Barring any late-breaking bug reports, I intend to finalize 8.42 as the formal release.  This means embedding the CRC value (to detect errors when loading a new ROS) and updating documentation for the current feature set and bug fixes.  I noticed that another device (BwG?) displays its version information on the title screen in the same location as ROS, meaning I need to remove it or move it.   I'll finish my pseudo-regression testing this weekend if I can find the time... 

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Hmm... would you believe I popped up that battery just for you to notice? <evil grin>

14 minutes ago, Ksarul said:

Just make sure the batteries are seated properly. . .the middle one looks like it popped up.

 

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On 1/30/2020 at 6:08 PM, Ksarul said:

Right now, four fully-populated cards exist. All are in the hands of testers (the last one will be enroute tomorrow). I plan on ordering the finalized boards in a week, as anything that goes out now will hit the board house during their local new year vacation. In between, I may finish assembling the rest of my test boards, as the number of required modifications is not huge. I'll also need to dump about $2,000 for the required memory chips, as my stock of those is relatively limited at the moment. I have enough 128K chips on hand to build about six more 2M boards and enough 512K chips to build three more of the 8M boards. As I said, limited on-hand chip stocks.

 

I expect that the final boards will be ready to sell by the end or March or early April.

Jim, if there is still a spot for me on the list, please add me to it.

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