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The Official NEO-GEO Thread!

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Charlie Cat Quadrunner

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Hi guys,

 

More from Pitfall Harry.

 

  1. #NeoGeo Pocket Color Handheld System Bundle Used BOX Included w/ 4 Games! #retrogaming #ebay http://www.retrodeals.net/KIOmyokLEt

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  2. SNK/#NeoGeo PROGEAR VINTAGE GAMING CONSOLE METAL SLUG KING OF FIGHTERS #retrogaming #ebay http://www.retrodeals.net/xFzKoiIrLM

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Metal Slug 2 -/#NeoGeo MVS - Tested and Fully Working #retrogaming #ebay http://www.retrodeals.net/pzimetUBaN

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Charlie Cat Quadrunner

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Hi guys,

 

去年年末のSNKさまのツイッターキャンペーンでポロシャツ当たったああああああああああああああああああああﾟﾟ+｡:.ﾟヽ(*´∀`)ﾉﾟ.:｡+ﾟずっとずうううううううううううっと大切にしますーーーー！！

Translated from Japanese by BingWrong translation?

Last year at the end of SNK's Twitter campaign polo shirt hit Ah Ah Ah Ah Ah Ah Ah Ah Ah Ah ° ° +. :. ° ヽ (* be ∀')-Lions. + ° Have been without uuuu uuuu uuu! and cherish will Skylar-.-!

 

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Charlie Cat Quadrunner

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Hi guys,

 

【メタルスラッグアタック】新キャラクターのクレオパトラ。 本編と関連の無いＭＳＡオリジナルイベント関連のキャラクターなので受け入れられるのだろうかと不安いっぱい。

Translated from Japanese by BingWrong translation?

[Metal Slug attack] new character Cleopatra. Will be accepted and this story not relevant MSA original event-related character, so full of anxiety.

 

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Charlie Cat Quadrunner

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Hi guys,

 

This afternoon were with Chastastic Gaming. Chastastic is new to the world of SNK and Neo-Geo gaming. So after having a good conversation on his comment channel, he was interested on taking in some video game requestsfrom me. To start things off, he picked Metal Slug Advance seeing that he had concerns on playing Neo-Geo titles onto this computer.

 

So let's see him play this game for the 1st time shall we? :)

 

From the description,

"Today I play Mission 1 of Metal Slug Advance on the Gameboy Advance (GBA) "

 

 

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Charlie Cat Quadrunner

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Hi guys,

 

La censure dans un jeu vidéo ici sur la jaquette de Nam1975 NeoGeo #RETROGAMING

Translated from French by BingWrong translation?

Censorship in a video game here on the cover of Nam1975 NeoGeo #RETROGAMING

 

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Charlie Cat Quadrunner

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Hi guys,

 

More from Pitfall Harry.

 

  1. KING OF THE MONSTERS Carton Box SNK/#NeoGeo AES ROM Japan FullyTested! #retrogaming #ebay http://www.retrodeals.net/srwEcDCZfS

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  2. #NeoGeo CD (Front Loading Type) Console JP GAME. #retrogaming #ebay http://www.retrodeals.net/TLymKzXHAp

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  3. #NeoGeo STICK 2 USB CONTROLLER PLAYSTATION 3 #retrogaming #ebay http://www.retrodeals.net/NMPbDdSQRt

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Charlie Cat Quadrunner

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Hi guys,

 

Continuing my series of irreverent #NeoGeo posts, my latest with the @retroist is wrestling title 3 Count Bout - http://www.retroist.com/2017/01/24/can-survive-3-count-bout-wrestling/ …

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Charlie Cat Quadrunner

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Hi guys,

 

Nous avons le plaisir d'annoncer que @furrtek sera au #HFS3 pour parler du reverse-engineering de la NeoGeo Patreon: https://www.patreon.com/furrtek

Translated from French by BingWrong translation?

We are pleased to announce that @furrtek will be the #HFS3 to talk about the reverse-engineering of the NeoGeo Patreon: https://www. patreon.com/furrtek

 

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Charlie Cat Quadrunner

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Hi guys,

 

https://www.patreon.com/furrtek

 

furrtek is creating SNK NeoGeo preservation code and hardware!!

 

furrtek is creating SNK NeoGeo preservation code and hardware
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Some would call this "a prototype". This isn't, since it won't lead to a product, but to the possibility of verifying accuracy of code and documentation. No one gets excited over some Verilog testbench that promises to run NeoGeo games. A board which runs cartridges without emulation is certainly more viable as a proof it really works.

Covers expenses for a 4-layer PCB, FPGA, RAM, flash, connectors, and assembly.
1 of 1
Your pledge will support a joint reverse-enineering effort to document and develop a complete open-source logic (think FPGA) definition of the SNK NeoGeo gaming console, for preservation. As well as an open-hardware FPGA verification board complementing it.

The emphasis on preservation means that there is no and will be no commercial production coming from me. Clearly: this isn't another miracle clone console project. It's about sharing files and designs which will perpetuate SNK's legacy.

Your donations will help compensate for my personal expenses related to research on this particular console: tools, helper and validation boards, components...

I will be posting important and detailed updates about progression with an interval of between 2 to 8 weeks, in parallel with Github commits (drafts, notes and code) here: https://github.com/neogeodev/NeoGeoFPGA-sim

Be sure to cap your pledge amount if you don't want to repeat donations in case I post multiple paid updates in the same month !

What I work with: Two AES home consoles (first and second chipset versions), MV1FZ and MV2 MVS slots, a few cheap cartridges for both type of systems, a Rigol scope which won't be needed often, an Open Workbench Logic Sniffer with 16 input extension (which might be replaced by a bigger memory LA), an Altera DE1 FPGA dev board, a Xilinx Spartan6 FPGA breakout board, a Wellon programmer, paper, too many pencils, and everything required to assemble stuff together properly.

A bit about me:
I'm a 27 year old guy from France messing with electronics and particularly 90's digital systems since about 10 years. I regularly contribute to the NeoGeo dev wiki along with other fanatics members with the aim to preserve the hardware I became obsessed with when I was a kid.

In the past, I produced small games and hardware which I sold by myself. That didn't go too well. Even though the games and hardware always worked as expected, my extreme lack of customer relations and delay management skills made it look bad.
This is why this project doesn't involve any customer-buyer scheme: you make a donation to help for a specific goal to be reached, which is described above.

Don't let the fact that some Metal Slug fakes came from the same country, and that our cheese stink as much as we do. We're always serious when talking about sticking a bunch of probes in a $200 console, scribbling lines on very wide graph paper, and writing uncomprehensible text files which turn numbers into video :]
RECENT POSTS BY FURRTEK
16015774559376222001.jpg?v=fuOkpw85Fao5-

 

 

 

Getting back to work on the project now that the move's over with.

Got the first die pictures of the revered YM2610 and started tracing some easy stuff.

Yamaha's FM logic isn't that obscure thanks to the work of other people. With these new pictures, it should be possible to know exactly how the ADPCM logic works.
I'll be posting annotated pictures of different zones to Github soon.

I didn't order the FPGA board in the end, as I didn't want to complicate things with the address change. Part of your last pledges went to @Johnmcmaster, who decapped and took the 2610 shots.

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The preliminary YM2610 ADPCM and timers code is on Github, and a few YM2610 were sent to someone who has hydrofluoric acid and a good microscope :)

Also sending the FPGA board to fab next week.

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Deus ex silicium huh ?
1
2m
@johndmcmaster ;)
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Q9Z8zvaMzL0pFCM26GRFK9eHks1KeOBZ3OYRXrsV

 

 

 

 

Didn't expect to get this part of the YM2610 done before the SSG ! Maybe because the SSG is mainly used just for the coin-in sounds...

Anyways, I shot this video a few days ago and didn't write a progress report here because I wanted to get the ADPCM-B to work (all ADPCM channels). I then realized it would take a few more days so here it is. There will probably be an small update to this, with the missing melody ;)

I will also update the Github repo later, since I'm using my Altera devboard right now and have to "port"/plug it to the main project.

MAME and the Japanese YM2610 datasheet were of great help !

Also, NEO-D0, NEO-F0 and PCM should be completly figured out.

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Fantastic work so far :D
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17678207176776026460.JPG?v=M8_ysMjdHkcQm
Spent 2 hours stripping a dead MV4 board I had since years.

This will greatly help verify and simplify logic for the NEO-D0, NEO-F0, and NEO-I0 chips.

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Shortly after the last post, I noticed that there was quite an important shortcut taken to get the system ROM to start the game: the Z80 wasn't running properly.

The system ROM didn't give the familiar "Z80 ERROR" because I previously put a loopback register in NEO-D0 so that the 68000 read back the command it sent to the Z80, bypassing it completly. So in saying that everything was working well enough for the game to start, I lied ;)

The Z80 is now working properly, as well as NEO-D0 so that the Z80 really replies to 68000 commands 1 and 3. It is also able to talk to the YM2610 to init its registers.

Lie cancelled :)

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Paid for by patrons·Oct 2, 2016 at 1:54am

12209238540877567797.png?v=wba9DGQnfTwXo

 

 

 

 

 

And I thought that I'd post updates 6 weeks apart at the very worst...At least I have some news to bring !

First of all, about the hardware: I will finally be ordering the 4-layer FPGA board as soon as the pledges for this update are processed. The components are still waiting in their trays for now.

I didn't get much done on the motherboard itself, as I wanted to dedicated some time to checks and to the addition of patch/bodge points on the FPGA board in case I mess up. That's done now.

Secondly, the real good news is about the Verilog code itself (see Github).The code is now accurate enough to run the system ROM (aka BIOS) up to the game's entry point !This may not seem that exceptionnal, but it really means that the logic and memories are working well enough to pass the self-tests and start executing game code.

As shown on the screenshot, the simulation log indicates that a jump to the game's entry point was taken after 220ms of what would be real time.If you're wondering why 220ms instead of the usual 3~4 seconds startup time of a real MVS board, it's because I patched the SP-S2.SP1 system ROM to greatly shorten memory test loops. If 256 bytes of RAM pass the test, no need to check the next 65280... This allows the simulation to be done in 10 minutes instead of many days of continuous computation.

The next step before letting the game run and see what happens would be to dump memories and compare the contents with a MAME snapshot under the same initial conditions.

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After almost a month long break, I'm getting back to probing boards with the aim of finishing the basics: Reset, watchdog, address decoding, and video sync. I'm still discovering new stuff !

The Github repo is still being updated accordingly: https://github.com/neogeodev/NeoGeoFPGA-sim


I also have to finish up the FPGA board and order it. Should be able to do that before july.

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Please contact me about the Virtual Boy. Still have not received any correspondence from you and I have tried contacting you via email & Skype.
7m
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17004814052233816564.png?v=ksB3Ko8_t37Wg

 


 

Back home, so just a quick post to show what I received from Avnet a few days ago.

As usual with big distributors, the parcel's size was inversely proportional to the component's.


From left to right: The CPLD which will replicate ZMC2 to save inputs on the FPGA, the FPGA, and its configuration memory.

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I knew two things would happen: ridiculous customs fees, and package that arrives just when I leave. As predicted, I got a $60 bill from DHL (on a $140 order), and their delivery guy arrived 2 hours after I left for a few days trip. Luckily he knew the address: he signed for me and left the package in the mailbox.

This means that I won't have pictures of the FPGAs and CPLDs before Wednesday. Oh well :)

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Amuse toi bien au stunfest :)
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After losing half my hair at attempting to make AO68000 work, I gave up and followed the advice I was given: switch to TG68K.

Great news: after less than a day of work, I got it set up good enough to make the MVS system ROM (BIOS) pass the work RAM test !


It isn't that much of an achievement after all, it only means that:

  • TG68K works
  • NEO-C1's logic is good enough to make SROM and WRAM access work
  • The read/writes to LSPC and a few other chips before the WRAM check also work

The next step is to find a way to check other access. This is a problem because the WRAM check alone requires almost an hour of simulation time.

A solution might be to patch the system ROM to skip the validated tests. In other words, split the boot process and check each part one by one.


The priority now is to order the parts for the FPGA board.
I'll try to get the BOM and order done before I leave next week. I'll be back home a bit after and will continue work on the video part.

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Hello, I am a bit disappointed that you did not use my 68000 core : the J68. It is in verilog, small, micro-programmed and French :-)
6m
Hello, I need to run the core at the original frequency. 3x would cause issues.
6m
Did you try to get everything written in verilog ? So you can run your sim under verilator ? With a fairly complex design (i.e. Amiga or 1943 core), I can simulate one frame per second on a core i7.
6m
The project itself is in verilog, only the 68k core I currently use is in VHDL. The problem isn't performance, but clocking. I want to stay with the 24MHz (12M for 68k) main clock. Anyways, the 68k core will only be part of the test board. The project files will only concern the NG itself. People will be free to plug in the core they want :)
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Paid for by patrons·Apr 30, 2016 at 6:18pm

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Is it May already ? This is a paid post. Thanks everyone for your support :)

Here are the latest news, what has been done and what needs to be done:


Regarding logic:

I recently moved blocks around NeoGeoFPGA-sim to make the NeoGeo core and auxiliary logic separation clearer, the goal is to simplify things when I'll need to make the design synthesizable for the verification board.

Elementary logic was added or refined in NEO-C1 such as mirroring ranges, unmapped zones, and wait state generation.

Two important additions which aren't directly NeoGeo related are video and audio interfaces: In an earlier post I wrote that I wanted to use an ADV7125 video DAC.


When recuding the outside world connections (FPGA I/Os), I realized that the count was still dangerously close to 200, and the 23 lines required for the ADV7125 weren't helping. Also, the ADV7125's regular steps between color intensity levels wouldn't be very faithful to the original NeoGeo ghetto R2R DAC.

Here's my solution: serialize the parallel color data in the FPGA, output the 3 serial streams, make them parallel again with 74VHC595 SIPO registers and feed their outputs to the R2R DAC.

Benefits: Saves 18 outputs. Rendering logic is untouched. Can exactly match the color levels of the NeoGeo.

Drawbacks: PISO/SIPO interface introduces a 0.5 pixel delay.

For the audio output, no change: it will be I2S for the planned AK4430 DAC.

No real progress on video, still have to figure out if the fix is rendered with a 4 or 8 pixels delay from fetch to display (not that hard).


Regarding hardware

:

More progress on the hardware as shown in the post picture: the FPGA SODIMM module is almost routed, and I might be able to order the board (x3) and parts at the end of the month.


To-do in May:

  • Some audio stuff: either get the PSG part of the YM2610 working, or the Z80 core and NEO-D0 Z80 handling.
  • Get the fix working with exact timings, make room for sprites.
  • Make the 68K core go past 2 instructions...
  • Finish FPGA module, switch motherboard to 2-layers.
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Talking with a friend about FPGA development boards made me realize how painful it would be to have the FPGA fail on the verification board, knowing it would be in BGA and next to a bunch of other components.

$400 isn't that steep of a price for such a project, but burning up 3/4th of it by accident would be a big disappointment for everyone.


To minimize the risks, I came to consider a two-board solution:

* A big 2-layers board with all the connectors, 68k work RAM, flash, level converters and DACs.

* A smaller 4-layers board with only the FPGA and its configuration memory.


Since only the FPGA requires a 4 layers board, it would be a waste to route everything else on the same big and expensive board. Furthermore, if the FPGA dies for some reason, only part of the system would need replacement (or a revision).


I was looking for some mezzanine connectors for that solution and couldn't really find reasonably priced and sized ones to route ~180 I/Os. 0.4mm pitch next to plastic is scary, and 3 pairs of $4 connectors isn't very cost efficient.

Then I came across SODIMM connectors: cheap, vertical versions available, 200 pins, and doesn't require another connector on the plugged board !


I need to re-evaluate costs, but I guess making a separate FPGA module and switching to 2 layers for the "motherboard" will easily save $50 and lots of stress during the smoke test :)

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Please contact me regarding the VB mod.
9m
Hello, I sent you an e-mail.
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12563245375005498589.jpg?v=rXUiSpbkMBH3b
Did some PCB work for the parts that won't be changing. Changed the 245 latches from SOIC to QFN to save space and reduce the board's size as much as possible.

Not sure if the memory card is a good idea, it stretches the board over 2cm.


No updates on logic for now.

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19002532256718007.png?v=YGXZ2rU1CWLjNSX0

 


 

 

 

 

 

 

 

 

 

 

 

 

 


 

 


 

 

 

 


 

Did some more component selection, most of the ICs are chosen.

Still nothing definitive, and the people making the IcoBoard informed me that their hardware might suit my needs. Decisions will have to be taken :)


Here's the current BOM if I chose to go for a completely custom board. Digikey part numbers are in parenthesis:

* XC6SLX16-2FTG256C (122-1672-ND) - Main FPGA

* XC9572XL-10TQG100C (122-1386-ND) - Graphics serializer CPLD, saves I/Os

* ADV7125 (ADV7125KSTZ50-ND) - Video DAC

* IS62C256AL-45ULI-TR (706-1310-1-ND) - Work SRAM

* SST39VF020-70-4C-WHE (SST39VF020-70-4C-WHE-ND) - SFIX ROM

* M29W400DT55N6E (M29W400DT55N6E-ND) - System ROM

 

* 74ALVC164245 (568-4985-1-ND) - 16bit level adapters/buffers

* 193-8MS (CT1938MS-ND) - Dipswitch

* A-DS 15 A/KG-T2S(AE10974-ND) - Joypad connector

* MD-90S (CP-2490-ND) - MiniDIN-9 A/V connector

* 345-100-520-201 (151-1301-ND) - Cartridge connector


Counting one part more than required for each, it sums up to $131.

I'm estimating power supply parts and passives to add $30 more.


 

Regarding the board itself, I've read Marshallh's BGA slides (again) and tried breaking out the FPGA: 4 layers is definitely enough !

I got an ad for Gold Phoenix's new 4-layer pooling service last week. The best deal I can get from them is $90 + $45 shipping (ouch) = $135 for one 6x3.4in board. PCBShopper gives about the same price for other Chinese board houses but for 5 boards and a stencil (nice !). OSHPark tells $205 for the same size and 3 boards.

 


TL;DR: The complete board will end up costing around $400. No surprises :)

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8261341556595229420.jpg?v=ArF3kFDjVf0XvV

 


 


 

 


 

 


 

In the previous post, I wrote about Wavedrom to draw chronograms from obervations, measures and notes. I was already getting slowdowns due to the size of the data (not that big) and finally got to the point it became unusable.

Instead of desperately trying to make Javascript and SVG rendering in Chrome faster, I spent these last 6 days writing a standalone Wavedrom clone in VB6, using OpenGL for rendering.


Here it is: https://github.com/furrtek/Waimea


This is really a side project to the NeoGeo stuff, but I'm sure I won't regret the time I spent making a tool that suits the needs.

It's stable enough to be used, so I can go back to REAL NeoGeo work now :)


I still want to get perfect fix timings before moving on to sprites, even if I gathered quite a lot of infos on sprites already.

I first thought the fix tiles were rendered with a 4 pixels delay (half a tile) after nametable lookup, but it's actually 8 (a full tile). This matches Charles mvstech.txt infos, and reminds me of those two back-to-back latches moving a tile number I saw on the Alpha68k months ago.


Sprites aren't too scary. The horizontal shrinking and odd/even pixels might be confusing at first, but nothing extreme.

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7378972499667105098.png?v=BuxHk0Tr1I4K0s

 

 


 


 

 



 

 

 

 

 


 


 


 

Representing chronograms in Notepad started to get confusing.

While searching for a graphic editor, I discovered Wavedrom . It's a js application able to parse specially crafted JSON files to render chronograms as SVG.


The waves are defined as strings, where each character represents a "block". So switching from the text drawings I had to that particular format was quick and easy.


 

The amount of SVG data generated can cause performance issues, so I might fork it to adjust some stuff for big chronogram sheets: mainly prevent automatic refresh (slow), adding more colors and also half-clock transitions. Will see where that goes...



 

 

In the meantime, enjoy the screenshot ;)

It represents most of what's going on just before and after a new video line starts. Graphics prefetch is done while CHBL is high, then active display starts.

 


The file with a few comments is found here: https://github.com/neogeodev/NeoGeoFPGA-sim/blob/master/wavedrom.json


I also wanted to thank everyone for their help. I'll be buying the first components for the validation board mid-April (FPGA, SRAM and flash). They'll come from Digikey, so I guess that a large portion of March's pledges will go to them (and to the customs office...).


I'm looking at the XC6SLX16-2FTG256, but I'm still not sure if I want to try HDMI or not. If so, I'll need either more I/Os to hook up an SDRAM framebuffer, or a magic analog-to-HDMI chip from Analog Devices. I certainly don't want to hack up the rendering logic to generate HDMI directly.

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Great stuff :)
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8297479686175943690.jpg?v=x6aLdiOKDA8Sjz

 


 

 

 


 

Instead of trying to guess the correct timings for the fix render cycle, I wired up the logic analyzer again and spent half the day recording everything between LSPC and B1. I now have 6kB worth of notes and many chronograms.


What comes up is just a confirmation that:

* The video logic is very simple compared to consoles of the time.

* Using both edges of a clock is crazy.


Now to match everything...

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13911220238061826589.jpg?v=ukIrxjf2Jd2v8

Slowed down verilog work after finally breathing some fresh air.

Did some component selection, and a bit of schematic and PCB work for the test board, since it will be made. Thanks to Marshall H. for helping.

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Paid for by patrons·Mar 10, 2016 at 7:55pm

 


 


 


2rw2lwl.pngw8ap09.png


 


 


 


 

...from a tilemap snapshot ;)


In the last post I was aiming at making ao68000 run at least up to the MVS checks. I actually got fed up of trying to debug a poorly documented core, so I switched to specific NeoGeo stuff instead for this month.


Since I believe this can also be seen as a milestone, I'm making this a paid update. Thank you everyone :)


2rw2lwl.pngw8ap09.png


As you can see, the output of the design is able to render the fix layer correctly. The complete screencap is from MAME, and the fix-only one is the output from the design, obtained by feeding it a virtual Joy Joy Kid cartridge and a VRAM dump from MAME.


This means that the data path and sequencing from the cartridge's ROM and tilemap in VRAM to the video output is good enough to be glitch-free.


This doesn't mean that all the timings are good yet. All memories are simulated by having the worst possible delays and most signals match those of a real NeoGeo, but some are passed between chips which should not, meaning that there are some simplifications to be done.


The next step will be to do more measurements on my AES to see what doesn't match, and correct my guesswork. Once done, ground will be clean enough to move on to sprites.

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These last days consisted of blind-writing verilog with inspiration from the neogeodev wiki and MAME's source. Started hooking up the ao68000 68k CPU core yesterday, to test bus control and address decoding.


The first step will be to have the system ROM run at least up to the MVS self-checks. This should happen shortly, as the only problem I have now is with understanding the 32-bit access done through the Wishbone interface.


I'll write a paid update when I'll be able to prove correct execution up to the checks.


github.com/neogeodev/NeoGeoFPGA-sim

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Anthony...

Edited by fdurso224
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Charlie Cat Quadrunner

+Charlie Cat

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Hey guys,

 

Back with TheDarkAce doing more great soundtracks for us. This time, its Billy Kane's theme history.

 

 

List of Billy Kane's themes, and pics will repeat


Billy Kane

Fatal Fury 1: Hashi wo Arukeba, Bo ni Ataru (Billy Kane) Theme (Neo-Geo) OST 0:36

Fatal Fury 1: Hashi wo Arukeba, Bo ni Ataru (Billy Kane) Theme (Neo-Geo) AST 3:38

Fatal Fury 1: Hashi wo Arukeba, Bo ni Ataru (Billy Kane) Theme (SNES) 6:40

Fatal Fury 1: Hashi wo Arukeba, Bo ni Ataru (Billy Kane) Theme (Sharp X68000) 8:42

Fatal Fury 2/Special: London March (Billy Kane) Theme (Neo-Geo) OST 10:27

Fatal Fury 2/Special: London March (Billy Kane) Theme (Neo-Geo) AST 13:29

Fatal Fury 2: London March (Billy Kane) Theme (Sega Genesis) 18:04

Fatal Fury 2: London March (Billy Kane) Theme (SNES) 22:05

Fatal Fury 2: London March (Billy Kane) Theme (PC Engine CD) 25:07

Fatal Fury Special: London March (Billy Kane) Theme (SNES) 28:48

Fatal Fury Special: London March (Billy Kane) Theme (Sega Game Gear) 31:08

Fatal Fury Special: London March (Billy Kane) Theme (PC Engine) 33:38

Real Bout Fatal Fury 1: N.D.R. (Billy Kane) Theme (Neo-Geo) OST 37:12

Real Bout Fatal Fury 1: N.D.R. (Billy Kane) Theme (Neo-Geo) AST 40:57

Real Bout Fatal Fury Special/2: London March (Billy Kane) Theme (Neo-Geo) OST 44:41

Real Bout Fatal Fury Special/2: London March (Billy Kane) Theme (Neo-Geo) AST 47:48

Real Bout Fatal Fury Special: London March (Billy Kane) Theme (Game Boy) 50:51

Fatal Fury Wild Ambition: The Long Pole (Billy Kane) Theme (PS1) OST 52:31

The King of Fighters '95: Arashi no Saxophone (Rival Team) Theme (Neo-Geo) OST 55:33

The King of Fighters '95: Arashi no Saxophone (Rival Team) Theme (Neo-Geo) AST 58:51

The King of Fighters '95: Arashi no Saxophone (Rival Team) Theme (Game Boy) 1:04:28

The King of Fighters '97: London March (Billy Kane) Theme (Neo-Geo) OST 1:07:06

The King of Fighters '97: London March (Billy Kane) Theme (Neo-Geo) AST 1:09:50

The King of Fighters 2002: Big Pain (Outlaw Team) Theme (Neo-Geo) OST 1:14:25

The King of Fighters 2002 Unlimited Match: Masquerade (Outlaw Team) Theme (XBLA) 1:16:42

The King of Fighters 2003: Villainous (Outlaw Team) Theme (Neo-Geo) OST 1:20:41

The King of Fighters 2003: Villainous (Outlaw Team) Theme (Neo-Geo) AST 1:24:24

The King of Fighters XIII: London March (Billy Kane) Theme (PS3/Xbox 360) 1:28:44

The King of Fighters XIII: Geese ni Kakatori (Billy Kane) Theme (PS3/Xbox 360) 1:33:05

The King of Fighters XIV: Soy Sauce For Koyadofu (South Town Team) Theme (PS4) 1:37:47

Fatal Fury 1st Contact: London March (Billy Kane) Theme (Neo-Geo Pocket) 1:42:40

The King of Fighters Kyo: London March (Billy Kane) Theme (PS1) 1:44:37

 

Anthony...

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