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4Anoid - Arkanoid conversion for the TI-99/4A


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because I don't remember whether wait states are variable, depending on the width of the memory bus, or always the same for all CPU memory access on the TI-99/4A. I also don't remember what the worst-case number of wait states on the 4/A is, 1 or 2. :dunce:

 

What do you mean by "width of the memory bus"?

 

The internal memory (0000-1FFF and 8300-83FF) is accessed directly by 16 bit without wait states; this amounts to 2 cycles for the memory access (1 cycle: setting the address bus, 1 cycle reading/writing).

 

All other memory locations are behind the databus multiplexer, i.e. two accesses with 8 bit. The datamux inserts 2 wait states per access; altogether you get 6 cycles for the external memory access. For each access by the CPU we get two accesses behind the datamux (also for byte operations).

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This was my second complaint about byte handling that CB is arithmetic.

It took me a long time to wrap my head around logical versus arithmetic on the 9900, but the above statement isn't really true. All C and CB do is a subtraction that discards the result (thus the result sets the status bits). All compares are both logical and arithmetic at the same time - you decide which you care about by selecting the appropriate jump instruction.

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This was my second complaint about byte handling that CB is arithmetic.

It took me a long time to wrap my head around logical versus arithmetic on the 9900, but the above statement isn't really true. All C and CB do is a subtraction that discards the result (thus the result sets the status bits). All compares (and MOVs for that matter) are both logical and arithmetic at the same time - you decide which you care about by selecting the appropriate jump instruction.

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It took me a long time to wrap my head around logical versus arithmetic on the 9900, but the above statement isn't really true. All C and CB do is a subtraction that discards the result (thus the result sets the status bits). All compares are both logical and arithmetic at the same time - you decide which you care about by selecting the appropriate jump instruction.

 

Yup, I misread the section on CB and conditional branches and wound up using only JGT and JLT, which are arithmetic. Per the E/A manual:

 

 

The CB instruction compares the two operands as signed, two's complement values

or as unsigned integers.

 

Well, that means that I need to test for LOGICAL "less than" and "greater than," the "L>" status bit, so which instructions do that?? Sections 7.5 through 7.9 handle this: JHE, JH, JL, JLE. Neat!

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What do you mean by "width of the memory bus"?

 

The internal memory (0000-1FFF and 8300-83FF) is accessed directly by 16 bit without wait states; this amounts to 2 cycles for the memory access (1 cycle: setting the address bus, 1 cycle reading/writing).

 

All other memory locations are behind the databus multiplexer, i.e. two accesses with 8 bit. The datamux inserts 2 wait states per access; altogether you get 6 cycles for the external memory access. For each access by the CPU we get two accesses behind the datamux (also for byte operations).

 

I meant “data bus”.

 

I know there is at least one thread here that discusses instruction timing for the 4A; but, I haven't yet found it. I always have trouble with wrapping my head around what is really going on with memory accesses (MAs) when I try to use the data and formulae listed in the TMS9900 instruction-timing section of the datasheet. How do the MAs in the table and what they contribute to the timing calculation in the formula relate to what you say above? A 0 wait-state value cancels the MA contribution to the formula.

 

...lee

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I am going to obsess over this routine for a while, and things are just not getting better.

 

I can cut it down dramatically at the entrance with

CAPMTN  CB   @CAPPOS,@CAPDST
        JEQ  CAPEND

I can even do a JH right away as the check for greater or less, BUT, then I have to increment or decrement @CAPPOS, whether it is in a register or still in memory. I can use INCT and DEC, but for a register I still have to right-justify and if I leave it in memory then I have two problems: the length of the instruction and that these instructions work on words not bytes. Then there is also the issue that I have a branch which winds up in the same place after manipulation. I could use AI like this:

CAPMTN  CLR  TMP1               * Prepare TMP1 for byte operation
        MOVB @CAPPOS,TMP1       * Pre-load TMP1 for later use
        CB   TMP1,@CAPDST       * Position = Desitination?
        JEQ  CAPEND             *  Yes, no motion, exit thread
        JH   CAPUP              * Position < Destination?
        AI   TMP1,>0200         *  Yes: increase position
CAPUP   AI   TMP1,>FF00         *   No: decrease position
        MOVB TMP1,@CAPPOS       * Update position
        LI   TMP0,>0304         * Letter Y-pos in SAL
        BL   @YVPUTB            * Put TMP1 in VDP RAM @TMP0
        LI   TMP0,>0308         * Capsule Y-pos in SAL
        BL   @YVPUTB            * Put TMP1 in VDP RAM @TMP0
    
CAPEND  B    @SLOTOK            * Exit thread

Using AI I think will give me the best balance of short and fast. The other thing I might do is modify the Spectra VDP put-byte routine to be able to use the high-order byte so that I do not have to worry about moving it around, though it might not matter in the end.* The problem is I want to use INCT and DEC, but cannot with the value I want to manipulate in the high-order byte, which it where it has to be for comparison.

 

(* Did this, now I can remove two SWPBs in my routine.)

 

Meh. I am going to work on this for another Rangers-Penguins half-period, then I am going to play with Ms. Pac-Man music, then chores.

 

EDIT: Then it hits me that I am not going to employ this routine in the game other than for the game selection screen, so the work here might just be misguided academics at worse or mental exercise at best.

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I meant “data bus”.

 

Thought so, nevertheless you don't actually have to care about it. The TMS9900 CPU only performs word accesses; AB, MOVB etc. only have an effect inside the CPU.

 

The data bus is 16 bit wide only for 0000-1FFF and 8300-83FF; all other accesses go through the databus multiplexer (except video).

 

The memory access (read) goes like this:

 

Cycle 1: Set the address bus lines.

Cycle 2: Check for READY=0. If not, read the values on the data bus lines. If yes, do nothing.

Cycle 3 ... 5: If cycle 2 had a READY=0, these cycles also have READY=0 due to the datamux operation. In the meantime, the datamux first sets A15 to 1, reads the byte into the latch, sets A15 to 0

Cycle 6: If we are here after the wait states, now READY=1, and the value of the second byte access is put on D0-D7, while the latch puts the stored values on D8-D15.

 

A similar process happens on write:

 

Cycle 1: Set the address bus lines and shortly after, the data bus lines.

Cycle 2: Check for READY=0. If not, command is complete. If yes, do nothing.

Cycle 3 ... 5: If cycle 2 had a READY=0, these cycles also have READY=0 due to the datamux operation. In the meantime, the datamux first sets A15 to 1 and sets the data bus, then sets A15 to 0 and data bus to the other byte

Cycle 6: If we are here after the wait states, now READY=1, and the command is complete.

 

However, most commands require a read-before-write, so we have to add the above cycles.

 

Accordingly, we have 0 or 4 wait states for reads and 0 or 8 wait states for (most) writes.

 

---

 

Execution time: T = time(cycle) * (C + W * M) with W=number of wait states

 

Example: Suppose we have an A R0,R1.

 

In the specs we have the add command (A) with base cycles C=14, memory accesses M=4, address mod for source and destination.

 

So how do we get these numbers in the table? We have 7 machine cycles @ 2 clock cycles ©:

 

1. Read instruction

2. ALU

3. Read source

4. ALU

5. Read destination

6. ALU

7. Write destination

 

On cycles 1, 3, 5, 7 we have memory accesses (so M=4). Each access may show a certain number of wait states. If we had indirect addressing, the address modification would add some more cycles.

 

If our command is in PAD RAM (with regs in PAD), we do not have wait states.This calculates as T = 333ns * (14 + 0*4) = 4.662 µs.

Now we have the same command in normal RAM (also regs in normal RAM). We get T = 333ns * (14 + 4*4) = 9.990 µs.

Edited by mizapf
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Using AI I think will give me the best balance of short and fast.

The best approach is to use AB and SB (not AI!), then store a >01 byte either a register (for faster access) or memory location (if you can't spare the register). For instance:

 

H01 DATA >0100
...
ADD1 AB @H01,@VARIABLE
SUB1 SB @H01,@VARIABLE

The other option is to ask yourself whether you really need to use bytes. Using words for your variables will nearly always be faster overall, because you can take a lot of shortcuts in the code handling. Yes, it doubles your memory usage and yes, it feels wasteful, but you'd be surprised how often you can actually get away with it. ;)

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The other option is to ask yourself whether you really need to use bytes. Using words for your variables will nearly always be faster overall, because you can take a lot of shortcuts in the code handling. Yes, it doubles your memory usage and yes, it feels wasteful, but you'd be surprised how often you can actually get away with it. ;)

 

 

I am manipulating the PAD RAM copy of the VDP sprite table. As the VDP is byte-oriented, the table is byte-oriented, and therefore my approach has been to work with bytes. For the demo I am not using a local sprite table just a couple of PAD RAM variables. For the game I could use a couple of word variables and worry about byte stuff when manipulating the sprite table, I suppose.

 

This is some real aggravating shyt but not insurmountable.

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I thought of another point. It seems I am limited for working with literal (iop) values in the 9900 instruction set. General addressing is abundant: I can work with registers, memory, memory pointed to by registers, memory pointed to by memory locations, and offsets with any. But I do not see a whole lot of instructions to work with immediate values. I suppose in the end that is not such a big deal since I am either taking a value from memory immediately following the instruction or somewhere else in memory.

 

So for my movement routine I am using AI because I can just write the ASM equivalent of "CAPPOS=CAPPOS-1" rather than "ONE=1; CAPPOS=CAPPOS-ONE." What am I missing here?

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The trick is to remember that there's very little practical differences between memory and registers, and use memory freely, like I suggested. To use AI, you need to get the value into a register, potentially do your byte->word extension (however you do it), do the add, and get the register back into memory. Using AB with the '1' value in memory at a label is a single instruction. The overhead is not even much worse - AI R0,>0001 needs to read two words for the instruction, read R0, then write R0 back for a total of four memory operations (ignoring the multiplexor and timing for now). AB @HEX01,@MYDATA reads three words for the instruction, one for HEX01, read MYDATA then write MYDATA back for a total of six.

 

If you already have the data in a register and you don't need to swap or shift it, the immediate math will win, but if you are just manipulating the sprite table, don't even bother to load it. You can test for common conditions (such as zero) just by checking the flags after the AB, and if you need better compares, CB is there too. You just need to set up a few values in memory to use against it.

 

For really common numbers I like to store them in registers to improve performance, but that can be a later pass.

 

Ultimately, though, the differences we are talking about at this point are small. Unless you're actually hitting performance limits, either way is going to be more than quick enough and it's not worth stressing too much over it.. :)

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In-line with this post, tonight I loaded the sound test cartridge onto my Super Space II module. I had alternating problems getting the on-board RAM and the E/A GROM to show up. Turned out I had a teensy problem with a dirty cartridge port.

 

post-27864-0-58653600-1421820305_thumb.jpg

Ick.

 

There are some other issues, but the short story is I got it working and was able to load the cartridge file via the CF7+ and run the sound test on real hardware.

 

post-27864-0-25929300-1421820593_thumb.jpg

 

I am very pleased with the results. I was also able to get a first draft of graphics demo running. VERY pleased :)

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As of this afternoon Taito Corporation has been made aware of this thread. I have asked official permission to continue with the project. I have seen far too many hobbyist projects killed off by rights-holders, so I am hoping the company will extend its blessing to me and my little endeavor.

 

(EDIT: Incorrectly identified the rights-holder in original message.)

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I'll either love or hate the results.

 

As of this afternoon Bandai-Namco games has been made aware of this thread. I have asked official permission to continue with the project. I have seen far too many hobbyist projects killed off by rights-holders, so I am hoping the company will extend its blessing to me and my little endeavor.

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Dear Alan,

 

Thank you for your inquiry.

 

While we thankfully reviewed your request, we are unfortunately unable to officially approve your use of Arkanoid. We would appreciate your understanding for our company's licensing policy.

 

Taking this opportunity, we thank you for your interest in our property. Your continuous support would be greatly appreciated.

 

Sincerely,

 

*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

Overseas Support Team

TAITO CORPORATION

*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

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I suspected that would be the case. Do they appreciate that this is/was being developed for a 30+ year old computer, non-commercial, and playable by maybe 50 people, tops?

 

Kind of bonkers that TI are totally comfortable with their hardware and software being emulated, yet Taito aren't. If you were planning to develop it for smart phones I could completely understand it.

 

My suggestion would be develop something that is in the spirit of Arkanoid (like a tribute) but isn't Arkanoid. It can have all the same features, power-ups, power-downs, etc. just be different graphics, and different title screen. As a poke in the ribs, call it Not Arkanoid, and refer to it in all development threads as Not Arkanoid.

 

Sorry that you got the result you did. I know you've put a lot of work into it. I was really looking forward to it.

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While we thankfully reviewed your request, we are unfortunately unable to officially approve your use of Arkanoid. We would appreciate your understanding for our company's licensing policy.

 

Maybe it is just an issue of naming? I can well imagine that companies will not agree to use their brand names, logos etc. even if they actually do not make money with them anymore.

 

Imagine you write a game called "Arkanoid" which turns out to be really, really bad. Other people may falsely assume that this was written by Taito, and that they obviously lost their aptitude to create good games.

 

I don't really believe whether Taito can disallow to write a game that is similar to a game of theirs. What if we call it "Ticlonoid" ("TI clone of Arkanoid") and use different colors, some new patterns and so on?

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I don't really believe whether Taito can disallow to write a game that is similar to a game of theirs. What if we call it "Ticlonoid" ("TI clone of Arkanoid") and use different colors, some new patterns and so on?

Hear hear. Would be good to keep the project alive.

 

Call it Frankenoid and have a Frankenstein boss in there somewhere!

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Dear Alan,

 

Thank you for your inquiry.

 

While we thankfully reviewed your request, we are unfortunately unable to officially approve your use of Arkanoid. We would appreciate your understanding for our company's licensing policy.

 

Taking this opportunity, we thank you for your interest in our property. Your continuous support would be greatly appreciated.

 

Sincerely,

 

*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

Overseas Support Team

TAITO CORPORATION

*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

 

 

I know this is going to be an unpopular opinion, but fuck'm and do it anyway.

 

*edit* Actually, I shouldn't say "fuck'm". Reading between the lines, it sounds like they are not asking you to stop but are simply stopping short of giving you official permission to go ahead. They're probably just stuck between their lawyers and their love of the retro gaming community.

 

Having said that: I still say do it anyway.

Edited by TheMole
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...

do it anyway, Taito do not understand that the game is for a retrocomputer and not for mobile phone... maybe the person that has answered to your question have 25yo and don't know what is TI-99! :D

 

anyway you should do it the same for our little community... you will not sell this program and our is only a little community TI.

 

over this, however, i must say that if the name must but different, i would like the one suggested by sometimes99er, or with a 4 added like: "4Arkanoid"

 

post-24673-0-63113700-1422383724_thumb.jpg

 

but i prefer Arkanoid as standard classic name becouse it is will be ;)

Edited by ti99userclub
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