Random question about GROM Ready Line

[gregallenwarner]

I just have a random question concerning one of the lines in the cartridge port.

 

According to the pinout, there is a "Grom Ready" or "GR" line in the cartridge port, which is meant to put the CPU on hold while the slow GROM devices are fetching their data. My question is, can a device plugged into the cartridge port use this "GR" line to put the CPU on hold whenever it likes? Or does this only get decoded into a hold signal when the TI is addressing the GROM port addresses? I've tried looking at a schematic of the console, but it's not immediately clear to me whether this line will stall the CPU at any given moment.

 

Thanks.

[+Ksarul]

I'm not sure on that one, Greg--this might be one of those answers that Gary (OPA) has up his sleeve though. . .he has a lot of esoteric knowledge that covers this kind of TI things.

[+mizapf]

The schematics tell the following:

 

The /GREADY is masked with the /GS signal, i.e. it is masked away when no access to 9800 - 9FFF occurs.

 

Generally, READY is only used for memory accesses. That is, it is ineffective outside of memory operations. (I had to learn that for the emulation in MESS :-) ). Of course, the TMS9900 nearly always accesses external memory, but the 9995 has internal RAM and actually ignores READY as long as it operated on-chip.

[gregallenwarner]

Thanks, mizapf. I enjoy learning some of the peculiarities of how this old hardware worked!

[Tursi]

GR has to be gated because GROMs actually hold the line active when they are idle -- it's less an active-low ready line than an active-high "data available" line.

 

Interesting on the 9995 -- so if you had code running on the internal scratchpad RAM, it would ignore READY? I guess that makes sense!

[+mizapf]

Yes, you can find that in the TMS9995 data manual.

2.3.1.3 Wait state generation

Wait states can be generated for external memory cycles, external CRU cycles and external instruction cycles for the TMS9995 using the READY input. A Wait state is defined as extension of the present cycle by one CLKOUT cycle. [...] Note that Wait states cannot be generated for memory cycles that access the internal memory address space or for CRU cycles that access the internal CRU address space, as the READY input will be ignored during these cycles.