Using the F18A with another computer than the TI-99/4A

[Dexter]

I’m about to buy two F18A’s, one for my “new” TI-99/4A, and one for my 65816 based homebrew computer MARC-2. As I said before, my intention is to write a few little machine language games for both systems simultaneously. So both having the same VDP, surely is a huge advantage. Even more because the F18A is becoming almost a standard in the TI community. Of course I’ve looked on Matthew’s site and on this forum, but I probably overlooked one or two things.

 

MARC-2 has a 3.3V data bus on the CPU side, and a 5V data bus on the RAM side. In between, there is a 3.3V but 5V tolerant CPLD. (XC95288XL) My question is, can I connect the F18A to the 3.3V side?

 

And just out of curiosity, who of you uses the F18A with another computer than the TI-99/4A?

 

*------

 

Although MARC-2 is 3.3V, it’s not the definitive destination for the F18A. I’m designing a new computer, MARC-3 (My Adorable Retro Computer version 3). It’s practically almost ready, except for the actual build. The main difference is that it will be modular, that is, I’ll use a ground plane, similar to the S-100 bus, and carts for the different parts of the computer system. The second difference will be that it’s running solely on 5V.

[Tursi]

Matthew and I talked a lot about running it standalone, but I never got around to it. I am still waiting for one to hook up to a Beaglebone, hopefully.

[Dexter]

I took a look at the specs of the beaglebone, all GPIO's are 3.3V. So you talked about that, I assume?

Edited April 22, 2015 by Dexter

[pnr]

And just out of curiosity, who of you uses the F18A with another computer than the TI-99/4A?

 

The MiniCortex I'm designing has an F18A. The MiniCortex is a eurocard sized SBC with a 9995 CPU and roughly modeled on the Powertran Cortex (schematics). It started out as an extended version of Stuart's breadboard design for the 9995.

[Tursi]

I took a look at the specs of the beaglebone, all GPIO's are 3.3V. So you talked about that, I assume?

 

Nope, unrelated discussions. That's my problem.

[Dexter]

 

The MiniCortex I'm designing has an F18A. The MiniCortex is a eurocard sized SBC with a 9995 CPU and roughly modeled on the Powertran Cortex (schematics). It started out as an extended version of Stuart's breadboard design for the 9995.

That looks very interesting! I hope to see more from it.

 

 

Nope, unrelated discussions. That's my problem.

Well, there clearly comes something good out of those "unrelated discussions"

[Tursi]

Mostly I'm just hoping to be able to do some semi-hardware testing, rather than build a new product.

[+Vorticon]

 

The MiniCortex I'm designing has an F18A. The MiniCortex is a eurocard sized SBC with a 9995 CPU and roughly modeled on the Powertran Cortex (schematics). It started out as an extended version of Stuart's breadboard design for the 9995.

Nice! Will it have some for of Basic in ROM? (I assume Powertran Cortex Basic). Also what about storage?

[matthew180]

The F18A buffers all input and most output (the data bus) through a 245 buffer:

 

http://www.onsemi.com/pub_link/Collateral/MC74LCX16245-D.PDF

 

The device has LVTTL I/O that is 5V tolerant. So in a word, yes, it will work with a 3.3V I/O system on both sides. The FPGA is 3.3V but does not have 5V tolerant I/O which is why I had to use the buffer.

 

As for using the F18A in other systems, I use it in my 99/4A, MSX1, and CV. It has been tested in a good number of systems (a somewhat complete list is on my website somewhere.)

f18a_minimal_v1.3.pdf

[Stuart]

Matthew, the version of the F18A with the longer pins - how much higher does it sit above the board? (Couldn't see a picture of that version anywhere.)

[Dexter]

Please discard

Edited April 25, 2015 by Dexter

[Dexter]

The F18A buffers all input and most output (the data bus) through a 245 buffer:

 

http://www.onsemi.com/pub_link/Collateral/MC74LCX16245-D.PDF

 

The device has LVTTL I/O that is 5V tolerant. So in a word, yes, it will work with a 3.3V I/O system on both sides. The FPGA is 3.3V but does not have 5V tolerant I/O which is why I had to use the buffer.

 

As for using the F18A in other systems, I use it in my 99/4A, MSX1, and CV. It has been tested in a good number of systems (a somewhat complete list is on my website somewhere.)

Thanks for the info Matthew. According to the datasheet of the W65C816S, Input High Voltage is VDD x 0.8. So I might use a 74HCT245 on the data bus to ensure proper operation. Would you agree on that?

 

Anyway, I ordered two F18A’s and I’m pretty excited about it. \o/

[matthew180]

@Stuart: About the height of a socket or standard header. I posted a photo in the F18A thread:

 

http://atariage.com/forums/topic/168968-f18a/page-33?do=findComment&comment=3225571

 

@Dexter: 5V * 0.8 = 4V. So if you are running the W65C816S with a 5V supply then the buffer I used on the F18A will not drive it's input. You need a dual-voltage level *shifter*, which TI makes a lot of. Or use a CPU that uses standard TTL I/O, in which case a logic level high is usually anything over 2V. The 74HCT245 also looks like it would work, but the only way to know it to try. Mixing logic families is also a pain.

[Dexter]

You need a dual-voltage level *shifter*, which TI makes a lot of. Or use a CPU that uses standard TTL I/O, in which case a logic level high is usually anything over 2V. The 74HCT245 also looks like it would work, but the only way to know it to try.

The '816 on MARC-2 runs on 3.3V, so there I should be OK, according to the LCX16245 datasheet. Do you know a dual voltage shifter, just out of interest. It probably will even work when the '816 is running on 5V, because those ratings are very conservative.

 

I guess, somehow I'll get it to work.

 

Mixing logic families is also a pain.

Indeed, amen to that.

[matthew180]

http://www.ti.com/lsds/ti/interface/voltage-level-translation-products.page

 

http://www.ti.com/lit/an/scea035a/scea035a.pdf

[Dexter]

http://www.ti.com/lsds/ti/interface/voltage-level-translation-products.page

 

http://www.ti.com/lit/an/scea035a/scea035a.pdf

Thank you Matthew, very helpful info.

[Dexter]

Today I finished porting Matthew's VDP routines to 6502 machine language.

I used the 6502 mode of the 65816, I can tell that I'm really spoiled from the 9900.

To give a little insight in two of the same routines, one for the 9900 and the other for the 6502:

 

9900

*********************************************************************
*
* VDP Multiple Byte Write
*
* R0   Starting write address in VDP RAM
* R1   Starting read address in CPU RAM
* R2   Number of bytes to send to the VDP RAM
*
* R0 is modified, but can be restored with: ANDI R0,>3FFF
*
VMBW   MOVB @R0LB,@VDPWA      * Send low byte of VDP RAM write address
       ORI  R0,>4000          * Set read/write bits 14 and 15 to write (01)
       MOVB R0,@VDPWA         * Send high byte of VDP RAM write address
VMBWLP MOVB *R1+,@VDPWD       * Write byte to VDP RAM
       DEC  R2                * Byte counter
       JNE  VMBWLP            * Check if done
       B    *R11
*// VMBW
 

6502

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; VDP Multiple Byte Write
;
; +vmbw dst, src, num
;
; dst      Starting write address in VDP RAM
; src      Starting read address in CPU RAM
; num      Number of bytes to send to the VDP RAM
;
; move memory down
;
; from = source start address
;   to = destination start address
; size = number of bytes to move
;
 
!macro vmbw .dst, .src, .num {
               lda     #<.src
               sta     from
               lda     #>.src
               sta     from+1
               lda     #<.dst
               sta     to
               lda     #>.dst
               sta     to+1
               lda     #<.num
               sta     sizel
               lda     #>.num
               sta     sizeh
 
               lda     #<.dst
               sta     port1           ; Send *lowbyte* (A7 to A0) of VRAM address
               lda     #>.dst | $40    ; | $40 to indicate a write (x1xxxxxx)
               sta     port1           ; Send *highbyte* (A13 to A8) of VRAM address
 
               ldy     #0
               ldx     sizeh
               beq     +
-              lda     (from),y        ; move a page at a time
               sta     port0           ; Write byte to VDP RAM
               iny
               bne     -
               inc     from+1
               dex
               bne     -
+              ldx     sizel
               beq     +
-              lda     (from),y        ; move the remaining bytes
               sta     port0           ; Write byte to VDP RAM
               iny
               dex
               bne     -
+
}
 

The computer is running at 8MHz without wait state, and the F18A has absolutely no problem with it.

Edited May 22, 2015 by Dexter

[TheMole]

That is all kinds of awesome!

[+retroclouds]

Impressive!

[matthew180]

Very cool. Do you have a website or anything where you are documenting the build?

[Dexter]

I started a blog once, but then never looked at it again. I'm going to change that into sort of a description of MARC-1 and MARC-2.

[Dexter]

Very cool. Do you have a website or anything where you are documenting the build?

I just finished a description: MARC-2 BLOG

If you want to know anything in particular, just ask.