juice2839 Posted October 23, 2015 Share Posted October 23, 2015 (edited) I have been looking around for a decent memory map of the CV and didn't see one. I looked at the hardware and came up with the one below. I added in the SGM bank switching too. All the info I have found says the VDS is at 40h - 7Fh, but I didn't get that after looking at the hardware. Are there any programmers out there that can take a look at this and tell me if this would be a pretty good setup for a coleco's memory layout and ports? Also does anyone have any idea were the AY-8910 gets addressed with the SGM? This memory map does not take into account most of the mirroring that happens in the I/O ports. I used the literal addresses that I figured out from the hardware (If they are completely correct). Thanks for any input. Also is BEh and BFh where the Adam maps the VDP? Super ColecoVision Memory Map 8K 0000h Colecovision Bios or Port 7Fh Bit 1 = 0 Ram 1FFFh Bank Switched 8K Ram Port 7Fh Bit 1 = 1 Rom 24K 2000h 8K above mirrored or Port 53h bit 1=0 mirrored ram 7FFFh Bank switched 24K Ram Port 53h bit 1=1 24k ram enabled 32K 8000h Cartridge Rom FFFFh Input/Output Ports 00h Reserved 7Fh Write 80h Controller_2_Enable Read/Write A0h Video Display Processor (VDP) DataPort Read/Write A1h Video Display Processor (VDP) RegisterPort Write C0h Controller_1_Enable Read E0h Controller_Read Write E0h Audio_Write ADAM COMPUTER? Read/Write BEh Video Display Processor (VDP) DataPort Read/Write BFh Video Display Processor (VDP) RegisterPort Edited October 23, 2015 by juice2839 Quote Link to comment Share on other sites More sharing options...
plbyrd Posted October 23, 2015 Share Posted October 23, 2015 You should check this out: http://adamwiki.info/Adam_Technical_Reference_Chapter_3_2 Quote Link to comment Share on other sites More sharing options...
juice2839 Posted October 23, 2015 Author Share Posted October 23, 2015 (edited) You should check this out: http://adamwiki.info/Adam_Technical_Reference_Chapter_3_2 Yeah... That's one of the pages I looked at. It has no data about the IO address for the VDP or any info about the CV, but thanks. http://adamwiki.info/Adam_Technical_Reference_Chapter_2_2.2#2.2.4_Video_Display_Processor_.28VDP.29 This has some info on it though. Looks like it has the same address I got elsewhere, but it does show that the sound is FFh write only on the Adam. I doesn't show the controller address though. I think I'll post this on the programming forum actually. Edited October 23, 2015 by juice2839 Quote Link to comment Share on other sites More sharing options...
Kiwi Posted October 23, 2015 Share Posted October 23, 2015 Do you have "cv programming.pdf"? In the very last 4 page have the memory maps information. Quote Link to comment Share on other sites More sharing options...
juice2839 Posted October 23, 2015 Author Share Posted October 23, 2015 Do you have "cv programming.pdf"? In the very last 4 page have the memory maps information. No, but I'll see if I can snag one. Thanks Quote Link to comment Share on other sites More sharing options...
juice2839 Posted October 23, 2015 Author Share Posted October 23, 2015 Do you have "cv programming.pdf"? In the very last 4 page have the memory maps information. Okay if your talking about this http://www.gooddealgames.com/articles/ColecoProgramming/cv%20programming.pdf It has no info on the last 4 pages about the input/output ports used. In the VDP section of that PDF they have a snippet of C+ that uses address BEh and BFh for the VDP, but that's not where it is physically addressed from what I figured out from the schematic. Unless they just use garbage programming and it works because the address is mirrored. Or am I missing something? Quote Link to comment Share on other sites More sharing options...
chart45 Posted October 23, 2015 Share Posted October 23, 2015 ask 5-11 or nanochess they know for sure what you looking for Quote Link to comment Share on other sites More sharing options...
+5-11under Posted October 23, 2015 Share Posted October 23, 2015 Just look at the schematic. Quote Link to comment Share on other sites More sharing options...
Kiwi Posted October 23, 2015 Share Posted October 23, 2015 (edited) Doesn't the processor just output, input data from it own pin? It has no access to VDP memory. VDP has it own memory pool to access to. Processor sends requests to the vdp. Input example: In ASM: in a,(bfh) ; get register value (COLECO BIOS: call 1fdch)Output example: In ASM: ld a, valueout (bfh),a ; set valueld a, register_numberadd a,80hout (bfh),a ; write value in registerSo it not mapped to the processor's memory map.EDIT: SGM info, http://atariage.com/forums/topic/203851-super-game-module-technical-forum/ Edited October 23, 2015 by Kiwi Quote Link to comment Share on other sites More sharing options...
juice2839 Posted October 24, 2015 Author Share Posted October 24, 2015 Just look at the schematic. I looked at this schematic http://www.atarihq.com/danb/files/colecovision.pdfit has some errors in it. I actually just went and traced out stuff myself. I trust myself, was just wondering why stuff that's online is wrong LOL Quote Link to comment Share on other sites More sharing options...
juice2839 Posted October 24, 2015 Author Share Posted October 24, 2015 Doesn't the processor just output, input data from it own pin? It has no access to VDP memory. VDP has it own memory pool to access to. Processor sends requests to the vdp. Input example: In ASM: in a,(bfh) ; get register value (COLECO BIOS: call 1fdch) Output example: In ASM: ld a, value out (bfh),a ; set value ld a, register_number add a,80h out (bfh),a ; write value in register So it not mapped to the processor's memory map. EDIT: SGM info, http://atariage.com/forums/topic/203851-super-game-module-technical-forum/ I understand how the VDP works.. My real issue is with the addresses BFh. It's a mirrored address, and seems like junk programming. Someone has to understand what I am talking about. When you address decode you have your enable line to your Rom, Ram, I/O device from the address decode circuit.. A 74ls138 in this case. Mapping it out puts the VDP at A0h and A1h. Using BFh would work, but that's slopping because it's a mirrored I/O location. If for some reason the hardware changed (we know now that it didn't) You could have a problem. Quote Link to comment Share on other sites More sharing options...
+5-11under Posted October 24, 2015 Share Posted October 24, 2015 I looked at this schematic http://www.atarihq.com/danb/files/colecovision.pdfit has some errors in it. I actually just went and traced out stuff myself. I trust myself, was just wondering why stuff that's online is wrong LOL I don't recall any errors with the memory mapping. Quote Link to comment Share on other sites More sharing options...
juice2839 Posted October 24, 2015 Author Share Posted October 24, 2015 I don't recall any errors with the memory mapping. I don't think there are any errors in the 74ls138 decode circuit. I just double checked it on the pcb. I think there might be an error on the joystick inputs, but I have not totally confirmed it. If I might ask what do you have for a I/O memory map? I think mine is correct except it depends on how you want to look at the decoding. I guess it would be the higher address that are true and lower addresses that are actually mirrored. Address lines A2-A3 are don't cares so it's not fully mapped. It would be nice to compare. Any idea where they map the AY-8910? Quote Link to comment Share on other sites More sharing options...
juice2839 Posted October 24, 2015 Author Share Posted October 24, 2015 (edited) Okay Revamped... This should be correct aside from not having the AY-8910 addresses...... Super ColecoVision Memory Map 8K 0000h Colecovision Bios or Port 7Fh Bit 1 = 0 Ram 1FFFh Bank Switched 8K Ram Port 7Fh Bit 1 = 1 Rom 24K 2000h-5FFFFh Expansion or Bank switched 24k Ram Port 53h bit 1=1 24k ram enabled 6000h -7FFFh 1k Ram mirrored or part of 24K Ram Port 53h bit 1=0 mirrored ram 32K 8000h Cartridge Rom FFFFh The I/O addresses again, but shown before mirroring...??? Input/Output Ports 00h Reserved 7Fh Write 9Fh Controller_2_Enable Read/Write BEh Video Display Processor (VDP) DataPort Read/Write BFh Video Display Processor (VDP) RegisterPort Write DFh Controller_1_Enable Read FFh Controller_Read Write FFh Audio_Write Edited October 24, 2015 by juice2839 1 Quote Link to comment Share on other sites More sharing options...
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