Question about to PIA chips..

[DavidMil]

Ok, I have discovered that I have two PIA chips. One has a Atari part number of:

CO12298, says it's a 6520A, and a date code of 8132

 

The other has a Atari part number of:

CO14795, says it a 6520, and a date code of 8252

 

Besides one being almost a year and a half newer, is there any difference in these two chips?

 

Thanks,

DavidMil

[Van]

AFAIK there isn't a functional difference, in fact even a 6521 is a drop-in replacement also. Between the 6520 and 6521 they improved the current handling on the inputs slightly, but the Atari was designed around the older specs so these improvements have no impact. The 6520A being the older of the two, is less likely to have any improvements. Really, the PIA is a industry standard LSI chip with no specific Atari related functions, used widely at the time.

Yogi

[Rybags]

Fairly sure all the PIAs in my XL/XEs are 6820 types... later on Atari seemed to second-source a lot more.

Early on didn't they tend to use a lot of 6502Bs direct from MOS ?

Edited April 27, 2017 by Rybags

[Van]

Fairly sure all the PIAs in my XL/XEs are 6820 types... later on Atari seemed to second-source a lot more.

Early on didn't they tend to use a lot of 6502Bs direct from MOS ?

OK so I found on a Rockwell datasheet (Sept 24 1993) that the 'A' indicates a 2MHz device and plain is a 1MHZ. So I would guess that the older CO12 chips were all 'A' versions and the newer CO14 chips were after fab changes when all generic 6520s were faster. Just a guess. No idea on 'B' models but MOS was an early second source of Motorola's 6820.

 

There may be other differences as the 400/800 mobos include pull-up Rs on PB lines but XL/XEs don't. But this could be related more to the use of Port B then the chips used, as the XLs are using the Port in output mode only, to control mem mapping.

Yogi

 

 

OTOH ArcadeComponents lists both CO #s as 6520As

http://www.arcadecomponents.com/catalog/item/3054735/2995570.htm

http://www.arcadecomponents.com/catalog/item/3054735/2995601.htm

So the only real difference is the stock # printed on them (?)

Edited April 27, 2017 by Van

[DavidMil]

So from what I am understanding, PortB on the XL/XE machines actually controls the Memory test too.

Is this an internal difference in the chip or an interpretation my the OS of what to do? On the old 800's

PortB was the same as PortA (just controlled different joystick ports).

 

David Milsop

[+DrVenkman]

So from what I am understanding, PortB on the XL/XE machines actually controls the Memory test too.

Is this an internal difference in the chip or an interpretation my the OS of what to do? On the old 800's

PortB was the same as PortA (just controlled different joystick ports).

 

David Milsop

 

As I understand it, it's a change to the OS. The PIA chip itself is the same in all the machines.

[Van]

On a stock XL PB bits 0,1 and 7 control Basic, OS and Self test, on an 130XE bits 2-5 control the extra 64K. The different RAM extensions use and re-use some or all the PB bits. It's the same PIA as on the 400/800.

 

The code running on the CPU writes to Port B setting or re-setting a bit, depending on what to access. So yes the OS has initial control over it but user code can take control as well. A program can for instance use the RAM 'under' the OS or Basic ROMS. Lots of games do this and won't run without disabling Basic before loading.

Yogi

[DavidMil]

Alright. My question has been answered. Thank you all for the feedback!

 

David Milsop

[Rybags]

Yep, PIA chip itself has no difference AFAIK. You should in theory be able to pull a PIA from early 800 and put into a late 130XE with no difference in operation.

 

The joystick role vanished with the XL, the bit usage varied as time went along though.

Common to all XL/XE PORTB:

- bit 7 controls Self Test Rom, 0 = present @ $5000 but only if the OS is also present, 1=Ram @ $5000 (or empty on 16K 600XL)

- bit 1 controls Basic Rom, 0 = present @ $A000 regardless of other bitsettings, 1=Ram @ $5000

bit 0 controls OS Rom, 0 = Ram or empty on 16K 600XL, 1 = OS present @ $C000-$FFFF except IO which always appears @ $D000-$D7FF, and noting that PBI signals can remap the FP ROM area $D800-$DFFF.

 

Unique to 1200XL - bits 2 and 3 were outputs which controlled status LEDs, these are changed dynamically by the keyboard IRQ to reflect character set and keyboard lock status. The program code is still present in later machines even though the functions don't exist and role of these bits changed.

 

130XE - the memory mapping system for >64K machines uses bits 2,3 to select an external Ram bank that can appear @ $4000-$7FFF, bits 4,5 choose whether the CPU and Antic see normal or extended memory at these addresses.

 

XEGS - bit 6 = 0 is used to switch in the Missile Command 8K Rom where Basic would normally appear but only if Basic isn't enabled.

[Rybags]

Additional - the 32in1 OS from Atarimax uses the Self-Test bit to communicate with the PIC which controls the upgrade (command to choose active bank, request reset etc.)

[Kyle22]

NecroBump:

 

Does anyone know how fast a joystick port A pin can be toggled low / high on a stock clock Atari? It would be a matter of CPU cycles / PIA speed and capacitors on the ports, I would think.

I am trying to do some Nikola Tesla stuff, and I need a short pulse duration around 1MHz frequency.

Can I even get close?

There are those who are much better at maths than me.

Thanks.

 

Edited December 31, 2021 by Kyle22
missing word.

[Rybags]

You won't get close.  1 MHz frequency = 2 million changes per second so even at 1 per cycle you'd not be there.

In the real world you might do something like a succession of STA and STX but you're at 1 change per 4 cycles then throw in DMA contention and jitter on top of that.

 

So best case scenario = about 450 KHz - DMA losses.

At that frequency the cycle or so of jitter for 0->1 transitions would probably not matter a lot given the fact that refresh cycles are causing similar problem.

 

I guess you could do a cycle counting exercise and code it such that you get a smooth known waveform that's aligned at the scanline or two scanline level.