TIPI - TI-99/4A to Raspberry PI interface development

[+mizapf]

It's a standard procedure in network management; I think it is also included in some protocols.

 

We might be able to fine-tune it, but for my tests, it proved to be good already. Normally, the reconnections should work with the first or second attempt (1+2 seconds); if the first delay is long enough, it should take only that first delay. When the TIPI is rebooted, things take much longer, and here, the doubling should well accommodate for different Raspberry types. I actually planned for an even shorter delay at the start, but it seems as if the TIPI takes a second by itself before reopening the websocket server.

 

I assume that the user does not want to log into the TIPI to speed up things or that we have random connection breakups; these are just the two scenarios of the reset behavior and the rebooting.

[+jedimatt42]

So, this is what I've been testing: https://github.com/jedimatt42/mame/pull/1

 

Seems to be working... I'm moving on now. 

[+InsaneMultitasker]

29 minutes ago, jedimatt42 said:

Seems to be working... I'm moving on now. 

Outstanding. Thank you to both you and @mizapf for digging into this and resolving the issue, especially with it being so 'random' and hard to pinpoint what was failing. Hooray!!

On 7/21/2024 at 9:44 PM, jedimatt42 said:

change line 109 (your line number may be a little different) from:

//#define LOG

 

I don't know if leaving the log enabled would be a problem(?) but I commented out the LOG entry and reinstalled regardless.  Figured I would mention this for anyone else that might have enabled the log.

[+jedimatt42]

I probably don't have log rolling configured for the websocket log, so best not to leave it on forever. Although it may actually get erased everytime the tipi.service restarts. 

[+FarmerPotato]

On 7/3/2017 at 11:55 PM, jedimatt42 said:

I intend to make a PEB version. I've avoided using signals on the sideport that are not present inside the PEB so it relocates more easily. RDBENA signal should be the only extra thing to drive, and the same or inverse of my control of the on board buffer.

 

Anyone have a KiCad template for the PEB card? I have the docs/dimensions/specs, but if anyone has already done the EDA work, it would save me a day of my life.

 

I have to figure out how to actually measure my 32k board outline and measure parts placement for this...

 

As for the Geneve... Master DSR is going to make that a pain. The Level 3 access to special files isn't going to work as I understand it because they don't translate down to the lowever level sector IO.

 

But, I'm sure I will try... I have a Genmod Geneve, and DSK1 of the TIFDC doesn't work in ? DSR/ROM-MAP mode ? so I doubt I'll succeed. Unless I can come to understand that. Michael has said I need to add decoding of AMD & AME address lines. But All of the Genmod documentation says otherwise.

 

I started the 32k project as a step to learning how to build this sort of thing, so that eventually I could build storage for my Geneve. That is still the long term goal.

 

-M@

I am searching for "KiCad template for PEB card".

 

Is there one out there, free for use?

[+jedimatt42]

I don't have a formal template, but I have an example peb card. 

 

https://github.com/jedimatt42/tipi/tree/main/hardware/tipi-peb/kicad

 

You could rip up what you don't want and make a template from it.

[RickyDean]

I have this,