Jump to content
IGNORED

OT: Mojo FPGA Board


Willsy
 Share

Recommended Posts

Didn't want to hijack any threads, so starting a new thread. If FPGA stuff aint your thang then you can stop reading now!

 

---------------------------------------------------------------------------------------------------------------------------------------------------------

 

Would be grateful if the resident programmable logic guru's could have a look over this Mojo FPGA board that I purchased:

 

https://embeddedmicro.com/products/mojo-v3.html

 

It uses a Xilinx Spartan 6 XC6SLX9 FPGA - whatever the hell that is!

 

Is it fairly powerful? Could I make (assuming I had the skills) say, a 6502 or 9900 out of it?

 

Ta!

  • Like 1
Link to comment
Share on other sites

That is the board I'm using to develop TIPI.

 

Their 'Lucid' language for getting started is nice.. Go through all the tutorials..

 

The thing is 3.3v all around, so I use a bunch of 74lvc245's powered by 3.3v source to shift down to a safe input signal level.

 

I chose that board to be an FPGA dev board, without all the trappings of VGA / HDMI / audio / etc... ports that some of the other boards have.

 

Googling a bit for FPGA 6502 projects, I see someone has done one up on a low end Xilinx Spartan 3 FPGA that has 1700 logic cells, The Spartan 6 on the Mojo has a little over 9000 logic cells.

 

So, I would think it should fit.

 

-M@

Link to comment
Share on other sites

Didn't want to hijack any threads, so starting a new thread. If FPGA stuff aint your thang then you can stop reading now!

 

---------------------------------------------------------------------------------------------------------------------------------------------------------

 

Would be grateful if the resident programmable logic guru's could have a look over this Mojo FPGA board that I purchased:

 

https://embeddedmicro.com/products/mojo-v3.html

 

It uses a Xilinx Spartan 6 XC6SLX9 FPGA - whatever the hell that is!

 

Is it fairly powerful? Could I make (assuming I had the skills) say, a 6502 or 9900 out of it?

 

Ta!

 

 

I've been working on the TI-99/4A implementation on this same chip on a different board with external SRAMs. The entire TI-99/4A, including my still bogus CPU, takes 48% of the capacity of the XC6SLX9. The CPU is not yet size optimised, need to get it working first... The CPU is perhaps just over 20% of the capacity of the FPGA.

 

I have synthesised the Scramble arcade game on the Papilio board, also using XC6SLX9, that took something like 70% and includes two Z80 cores plus a whole host of other stuff. Quite a lot of stuff can be fitted in these chips.

  • Like 1
Link to comment
Share on other sites

...

Would be grateful if the resident programmable logic guru's could have a look over this Mojo FPGA board that I purchased:

...

For the price that Mojo board is a little lacking. You can get a lot of devboard for little money these days, and I recommend something with a few LEDs, buttons, some external memory, maybe a video jack of some sort, etc. This is a nice board for the price (but sadly currently out of stock):

https://numato.com/mimas-v2-spartan-6-fpga-development-board-with-ddr-sdram/

 

Spend some time looking around. You will quickly learn which boards have the expensive FPGAs on them, what is a decent set of features, etc.

 

It uses a Xilinx Spartan 6 XC6SLX9 FPGA - whatever the hell that is!

 

It is a Spartan-6 LX9 FPGA by Xilinx... ;-) The Spartan-6 is the next generation in the Spartan line. Not sure what you are looking for exactly. The Spartan-3 and Spartan-6 are the low-budget FPGAs from Xilinx, and these days the Spartan-6 is just as cheap as the Spartan-3, but with a lot more resources. The best way to know what it is would be to download the datasheets and start reading. Xilinx has awesome docs by the way, which is one of the main reasons I stay with them.

 

Is it fairly powerful? Could I make (assuming I had the skills) say, a 6502 or 9900 out of it?

FPGAs are really measured in logic-cell density more than "power", per se. Yes, the LX9 is more than capable of doing a 6502 or 9900. You can do a whole 8-bit or 16-bit SoC on the LX9 easy. If that is your goal, I would recommend you use CPU cores (see opencores.org) made by others until you get a grip on things. CPUs are interesting beasts and not as trivial as you initially think. From a software perspective, writing a CPU core is kind of like writing a compiler.

 

VGA video is easy to get working, at least from the standpoint of getting the right signals to the monitor to make it sync up and display pixels. But even before that, a blinking LED is the "hello world" app for FPGAs. So do that first. Also, I don't recommend you put anything between you an Verilog or VHDL. Short-cuts won't get you anything IMO. FPGAs are a fun ride, so enjoy it. :-)

 

If you have questions, post them. It easier to answer specific questions with code attached.

 

 

...

The thing is 3.3v all around, so I use a bunch of 74lvc245's powered by 3.3v source to shift down to a safe input signal level.

...

THIS!! I forgot to mention this in my previous post in the other thread, but most of the FPGAs you will be working with DO NOT HAVE 5V I/O!!! You MUST use level-shifting when trying to interface legacy TTL (i.e. 74 logic, etc.) or you risk blowing the I/O on your FPGA. You will find that there are no fewer than 10 Trillion options for level-shifting, all of them confusing with no clear-cut answers. If you can manage a direction pin, then using a dual-voltage 245 buffer (similar to what jedimatt42 cited) is recommended. There are "transparent" shifter options, but they always have trade-offs. I used a 3.3V 245 buffer on the F18A, but I wish I had used a dual-voltage version since it can be blown due to spikes on the 5V side (eg. people turning their systems off and on too fast.)

  • Like 1
Link to comment
Share on other sites

I swear, I had the 74lvc245 chips sitting here staring at me, while I examined the data sheet super confused. And I assumed a logic level shifter would require dual voltage rails. I just couldn't figure out how the thing was supposed to be used, until the term 5V tolerant finally struck a chord.

So, the one I cited is simply 5v tolerant, on inputs, and outputs are at the VCC level (3.3v)... 3.3v is sufficient to signal high for 5v TTL (unless you have other problems)

I blundered into this.

They do make chips that actually have a VCCA and VCCB so one side can output 5V while the other side outputs 3.3V when switching directions.. SN74LVC8T245, but I haven't found any that were PDIP.

Also, I second not sticking with Embedded Micro's Lucid language. Firstly, you only get the examples they offer, while the internet is full of verilog examples. Lucid was however, a friendlier environment to get a mental handle on some principles without getting Xilinx ISE involved. After running the tutorials in Lucid, I then worked through Embedded Micro's verilog tutorials in ISE, and have stuck with that.

Things I learned with a big struggle:

1. Block RAM won't synthesize unless you use the primary clock signal for the FPGA. I really wanted to clock it on the TI's memory enable signal. But that synthesized to logic units as a result.
2. Verilog include files should use ifndef macros like you do in C/C++ header files.

I have a ton more to learn. Really just getting started. The thing I really want to learn next is how to debug the chip with JTAG. LEDs are handy, and a physical logic analyzer is handy, but I only have a 1.5 channel tek device ( it was a free gift, that I love! 2nd channel only works sometimes :) and I barely know how to use it ) But ISE has ChipScope, https://www.xilinx.com/products/design-tools/chipscopepro.html

---

I would be interested in knowing why VHDL vs. Verilog in your guys' opinion?

---

You know what would be cool, if some of you experienced FPGA guys would publicly rip apart my code :) Point out things I'm sure I've done horribly... and what the better practice is.

This is simple glue logic for TIPI providing memory mapped IO to a raspberry pi with shift register based GPIO on the PI side, and memory mapped bytes on the TI side. I've rewritten it recently on this branch 'serialInput' so that it is manageable and readable, and it has real inconsistency issues, I assume because I'm not controlling the memory ready signal on the 9900 when the latches are being updated, but I also sometimes get a storm of garbage when reading and no latched state is changing. So I know there are things falling short of best practice. (far short)

https://github.com/jedimatt42/tipi/tree/serialInput/cplds/mojo-ise/src

mojo_top.v
crubits.v
latch_8bit.v
rom.v
shift_pload_sout.v
shift_sin_pout.v

(there are other files in there, that I didn't write. they were gifted to me from the sample ISE project from embedded micro for interacting with the AVR on the Mojo board. I will clean them out tonight.)

-M@

Link to comment
Share on other sites

Oh, this reply could go on for a while... But it is late and I need to sleep, so it will be brief with more detail to follow as necessary.

...
So, the one I cited is simply 5v tolerant, on inputs, and outputs are at the VCC level (3.3v)... 3.3v is sufficient to signal high for 5v TTL (unless you have other problems)
...


There are tons of "level shifters". Just look at TIs offerings on Voltage Translation to be even more confused and overwhelmed:

http://www.ti.com/lsds/ti/logic/voltage-level-translation-overview.page

You can get all kinds, and picking the right solution is not easy. I have a bunch of different kinds I have bought for testing. 5V *tolerant* does not mean it outputs 5V levels, and as you mentioned 3.3V logic is typically enough to drive 74LS TTL, but not always. Also, LVTTL (you will see this in FPGA datasheets) does NOT mean 5V tolerant! I found that out the hard way too.

...
They do make chips that actually have a VCCA and VCCB so one side can output 5V while the other side outputs 3.3V when switching directions.. SN74LVC8T245, but I haven't found any that were PDIP.
...


That's what TSSOP breakout boards are for:

https://www.adafruit.com/product/1206

You can get breakouts in many variations. SMD is not hard.

Also, I second not sticking with Embedded Micro's Lucid language. Firstly, you only get the examples they offer, while the internet is full of verilog examples. Lucid was however, a friendlier environment to get a mental handle on some principles without getting Xilinx ISE involved. After running the tutorials in Lucid, I then worked through Embedded Micro's verilog tutorials in ISE, and have stuck with that.


There are tons of examples all over the Net, also, the books I recommended... I recommend them. ;-) Read HDL, don't take one example as gospel. I started with ISE and did not find it that hard for a beginner to work through, once you get a basic idea of what you are doing.

Things I learned with a big struggle:

1. Block RAM won't synthesize unless you use the primary clock signal for the FPGA. I really wanted to clock it on the TI's memory enable signal. But that synthesized to logic units as a result.
2. Verilog include files should use ifndef macros like you do in C/C++ header files.


1. Actually you can, I did it just the other day. I don't have time to explain now, but I can post an example later.

2. I can't really comment on that, but using ifdef/ifndef, etc. in HDL sounds like a bad idea to me. Don't treat your HDL like C/C++ or any other software language. I have never used conditional inclusion / exclusion of HDL. I'm not sure why you would?

I have a ton more to learn. Really just getting started. The thing I really want to learn next is how to debug the chip with JTAG. LEDs are handy, and a physical logic analyzer is handy, but I only have a 1.5 channel tek device ( it was a free gift, that I love! 2nd channel only works sometimes :) and I barely know how to use it ) But ISE has ChipScope, https://www.xilinx.com/products/design-tools/chipscopepro.html


AFAIK ChipScope costs money. Debugging via JTAG would be great, but takes a bit to set up. Serial over USB works too. Or just a lot of LEDs. :-) Simulation is awesome and I highly recommend you always simulate your HDL to make sure it is doing what you think. Hardware is hard, that's why it is called hardware. ;-) Just like anything, it takes time to learn and get it right. Over time your designs will get better and things will work out faster, better, easier, etc.

 

As for logic logic analyzers:

http://dangerousprototypes.com/docs/Open_Bench_Logic_Sniffer

I have one and it works really well. You get them for about $40 from SeeedStudio.

---

I would be interested in knowing why VHDL vs. Verilog in your guys' opinion?

---


I think you found my post about that. I also just discovered that VHDL is really a subset of ADA, and I have discovered that ADA is really freaking awesome (http://cowlark.com/2014-04-27-ada/index.html) and I now like VHDL even more. :-) The more Verilog I read, the less I like it. IMO Verilog has too many nuances and you can get in trouble very quickly without realizing it. Also, one statement can do a lot of describing, and it is not always obvious.

You know what would be cool, if some of you experienced FPGA guys would publicly rip apart my code :) Point out things I'm sure I've done horribly... and what the better practice is.


Given unlimited time someone might do that. However, you will usually get better results if you pick out specific pieces yourself to post questions about. Just one topic could take many posts of conversation, and learning HDL takes time (I'm still learning a lot myself, and I've been at it since 2011).

 

Link to comment
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

Loading...
 Share

  • Recently Browsing   0 members

    • No registered users viewing this page.
×
×
  • Create New...