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The Inside Story of Texas Instruments’ Biggest Blunder: The TMS9900 Micropr


Willsy

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  • 5 years later...
On 6/24/2017 at 7:39 AM, JamesD said:

I think he accurately pointed out the flaws in the 9900 architecture and in bringing the chip to market.
I don't know that he was hostile towards the chip or the process that created it, but there seemed to be a negative tone to the article.

The TI-99/4 wasn't discussed in much detail, but I get the impression he saw it as the continuation of a failed strategy behind the 9900.
There were a couple factual errors, but he probably told the story as he saw events.

If TI hadn't tried to directly copy their existing CPUs almost exactly, I think the 9900 would have been much more competitive.
They should have moved the registers inside the CPU, added a stack pointer & related instructions, they should have created a 16 bit chipset in parallel with the cpu, and they should have added some sort of segmented addressing for a 24 bits address buss. Just eliminating all the extra memory cycles for external registers would have made the 9900 what? 20% or more faster?

As long as you stick with the same register model (other than stack usage) existing compilers and interpreters could have easily been ported to the new CPU and possibly even simplified..
If the stack push/pull instructions support saving multiple registers with a single instruction like the 6809, and interrupts either don't save any registers automatically or only a couple, then interrupt latency wouldn't be a problem either. It would be more than made up for over the 9900 by using internal registers anyway.
There are a couple odd looking things in the 9900 instruction set, but with the above changes it would have been way ahead of the 8086/8088.

After reading that article and the previous post, I get the impression that GPL was designed for the video game console.
The computer guys probably got saddled with it when the two divisions merged.
Strictly for video games I can see where they were coming from.
The story about the designers wanting a GPL cpu make more sense as well. Something cost reduced for a video game console maybe?
They wanted a custom CPU and TI said we already have a CPU, take it.
It would at least partially explain the closed design and marketing strategy of the TI-99.
The computer inherited the marketing strategy for the video game console.
I'm guessing it also inherited it's managers when the projects merged.
The question I have about the Milton Bradley story, is then how did TI end up with the software?
If all TI designed was the hardware, the software should have belonged to Milton Bradley.
There are some missing pieces to the story.

In 1977-1979, it would make no difference in performance considering SRAM chips, especially the 16 bit ones, were able to keep up with the CPU. Intel, in fact, borrowed a page from the TI-99/4 and 4A. Take a look at the 386 and 486. An Intel x86 processor did not directly accessed the main memory. They interfaced through a memory controller. However, it directly accessed a memory called cache memory. This would be roughly equivalent to scratch-pad memory that TI devised. This became beneficial when today's processors were too fast for system memory.

 

Back with the 386, that system memory would be DRAM because they were cheaper and provided more memory per dollar but they are slower. Current DDR5 SdRam is still a type of DRAM. SRAM would be faster but still too slow for efficient cache of L1/L2 level but was for L3 until more recently, when it was still an external chip on the motherboard. The 286/386 would not have on-die cache. It would be external SRAM. They were maybe 4k or 8k early on and increased to maybe 128kb. In 1979, 256 bytes was a sizable SRAM. If they had put 2KB or 4KB, it would have been extraordinary.

 

By 1979, they should have had 16 bit address lines for 128KB. They should have included a MMU/memory controller to allow internal or external RAM expansion of maybe 1 to 2 MB.  TI would have to upgrade to an 80 pin package by 1980/81. This would then allow the design for direct addressing more memory but the whole computer system upgraded to be able to facilitate a lot more memory than the TI-99/4A ended up being. Additionally, a full-size keyboard comparable to the IBM PC at the time. Cartridge port maybe moved to the back or facing upward. A side port could remain and PEB being a tower can (which some TI PEB owners ended up doing anyway), and include it as part of the package.

 

In this case, focus on competing with Apple II and IBM PC instead of trying to compete against Commodore so directly on the low end. Further improvement would be for TI to increase the speed to twice to four times the current speed. It would compete with 8086 and 286. Add pre-fetch and deep pipeline, and the chip can perform competitive to the 386 and 486. Eventual architecture upgrades to address the evolving market. Possibly evolving to an architecture that can switch between 16 bit and 32 bit and 64 bit. A modern 64 bit TMS 9900 with deep pipeline and on-die scratch pad memory can be incredibly fast, require a fraction of the transistors in the x86-64 chips of today and huge multi-core counts within the footprint and transistor count of a 12th generation i9. The key is to have scratch pad memory that keeps up with the cpu. Deep pipelining the bus can speed things up regarding effective clock cycles an opcode instruction requires to perform. The 6502 was already pipelines to some extent in a sense of being some kind of prefect pipeline of sorts. TI did some kind of prefect pipeline in a successor model of the TMS99XXx series.  The TMS9900 had impressive context switching because it was designed around the TI990 which was designed for multitasking. DNOS and DX10.

 

Which had they not over compromised the cpu and computer architecture, they could have potentially have a computer with networking, multitasking from their DNOS and DX10 and give it a GUI by 1979 or 1980. The video chip was duly capable. As well, they could have the genlock fully function in the consumer production. They were, after all, putting a minicomputer into a microchip. They had something that could rival an Amiga operating system, albeit on a less colorful graphic chip. With a video card in the PEB, they literally could rival Amiga and PC for years. 

 

They didn't it out as well as they could have. Imagine being able to have the scale and potential of TI-990 on a microcomputer that could serve and upgradeable for 8 to 10 years with future upgrade models that can upgrade out for 10 years introduced every 3-5 years. Same OS platform with upgrades/updates.

 

 

 

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1 hour ago, Wildstar said:

In 1977-1979, it would make no difference in performance considering SRAM chips, especially the 16 bit ones, were able to keep up with the CPU. Intel, in fact, borrowed a page from the TI-99/4 and 4A. Take a look at the 386 and 486. An Intel x86 processor did not directly accessed the main memory. They interfaced through a memory controller. However, it directly accessed a memory called cache memory. This would be roughly equivalent to scratch-pad memory that TI devised. This became beneficial when today's processors were too fast for system memory.

 

Back with the 386, that system memory would be DRAM because they were cheaper and provided more memory per dollar but they are slower. Current DDR5 SdRam is still a type of DRAM. SRAM would be faster but still too slow for efficient cache of L1/L2 level but was for L3 until more recently, when it was still an external chip on the motherboard. The 286/386 would not have on-die cache. It would be external SRAM. They were maybe 4k or 8k early on and increased to maybe 128kb. In 1979, 256 bytes was a sizable SRAM. If they had put 2KB or 4KB, it would have been extraordinary.

 

By 1979, they should have had 16 bit address lines for 128KB. They should have included a MMU/memory controller to allow internal or external RAM expansion of maybe 1 to 2 MB.  TI would have to upgrade to an 80 pin package by 1980/81. This would then allow the design for direct addressing more memory but the whole computer system upgraded to be able to facilitate a lot more memory than the TI-99/4A ended up being. Additionally, a full-size keyboard comparable to the IBM PC at the time. Cartridge port maybe moved to the back or facing upward. A side port could remain and PEB being a tower can (which some TI PEB owners ended up doing anyway), and include it as part of the package.

 

In this case, focus on competing with Apple II and IBM PC instead of trying to compete against Commodore so directly on the low end. Further improvement would be for TI to increase the speed to twice to four times the current speed. It would compete with 8086 and 286. Add pre-fetch and deep pipeline, and the chip can perform competitive to the 386 and 486. Eventual architecture upgrades to address the evolving market. Possibly evolving to an architecture that can switch between 16 bit and 32 bit and 64 bit. A modern 64 bit TMS 9900 with deep pipeline and on-die scratch pad memory can be incredibly fast, require a fraction of the transistors in the x86-64 chips of today and huge multi-core counts within the footprint and transistor count of a 12th generation i9. The key is to have scratch pad memory that keeps up with the cpu. Deep pipelining the bus can speed things up regarding effective clock cycles an opcode instruction requires to perform. The 6502 was already pipelines to some extent in a sense of being some kind of prefect pipeline of sorts. TI did some kind of prefect pipeline in a successor model of the TMS99XXx series.  The TMS9900 had impressive context switching because it was designed around the TI990 which was designed for multitasking. DNOS and DX10.

 

Which had they not over compromised the cpu and computer architecture, they could have potentially have a computer with networking, multitasking from their DNOS and DX10 and give it a GUI by 1979 or 1980. The video chip was duly capable. As well, they could have the genlock fully function in the consumer production. They were, after all, putting a minicomputer into a microchip. They had something that could rival an Amiga operating system, albeit on a less colorful graphic chip. With a video card in the PEB, they literally could rival Amiga and PC for years. 

 

They didn't it out as well as they could have. Imagine being able to have the scale and potential of TI-990 on a microcomputer that could serve and upgradeable for 8 to 10 years with future upgrade models that can upgrade out for 10 years introduced every 3-5 years. Same OS platform with upgrades/updates.

 

 

 

Personally, if I was designing the system, I would have engineered it with a slot for scratch pad (sram) that would have the address lines for 20 bits addressing of 16-bit addressing. Effectively expandable to 2 MEGABYTES by using all of pins with none of them being n.c. on the 64 pin DIP. I would have provide for 32 bits of addressing in the memory addressing. I would have a slot for the DRAM system memory that would allow for 32 bits worth of 8-bit addressing... even if the unit came stock with much less than that. The mixing would have been an interesting task but I doubt the cost that much... maybe 10 to 20% increase in manufacturing cost but would have allowed for that much more in upgradability. Paving way to making a full TI-990 in desktop pc scale form factor and putting in a lightweight WIMP shell for a DNOS based OS/kernel. The video chip in the TI-99/4A was in itself more than sufficient to do that. A full feature keyboard as those available and used by the TI-990 terminals and all would have placed such a system highly competitive against IBM PC and fair well against Apple II as well. The TI-990 basis for the TI-99/4 and 4A was actually a bit too much compromises needed to compete with the Atari and TRS-80... and the VIC-20 when that came out. Trying to push to too low of a price mark to fight a much simpler computer system which were more limited, targeting a market that would allowed market of upgrades and usability for more than a decade. Later, implementing more powerful graphics via video card in the PEB tower. Now I need a time machine that works.

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11 minutes ago, Wildstar said:

Personally, if I was designing the system, I would have engineered it with a slot for scratch pad (sram) that would have the address lines for 20 bits addressing of 16-bit addressing. Effectively expandable to 2 MEGABYTES by using all of pins with none of them being n.c. on the 64 pin DIP. I would have provide for 32 bits of addressing in the memory addressing. I would have a slot for the DRAM system memory that would allow for 32 bits worth of 8-bit addressing... even if the unit came stock with much less than that. The mixing would have been an interesting task but I doubt the cost that much... maybe 10 to 20% increase in manufacturing cost but would have allowed for that much more in upgradability. Paving way to making a full TI-990 in desktop pc scale form factor and putting in a lightweight WIMP shell for a DNOS based OS/kernel. The video chip in the TI-99/4A was in itself more than sufficient to do that. A full feature keyboard as those available and used by the TI-990 terminals and all would have placed such a system highly competitive against IBM PC and fair well against Apple II as well. The TI-990 basis for the TI-99/4 and 4A was actually a bit too much compromises needed to compete with the Atari and TRS-80... and the VIC-20 when that came out. Trying to push to too low of a price mark to fight a much simpler computer system which were more limited, targeting a market that would allowed market of upgrades and usability for more than a decade. Later, implementing more powerful graphics via video card in the PEB tower. Now I need a time machine that works.

Further, even if I couldn't provide the address lines, they'd be reserved so a cpu chip drop-in upgrade could be made and may include additional instruction opcodes of later TI-990 from that in the original 990/4, 5, 9 models such as the 10, 10A, 11, and 12 had with maybe exclusion of TILINE features unless that can be implemented without externally of processor chip itself... even if implemented on a smaller connector in some fashion. Some models seemed to indicate that possibility. In ways, my spec might even go beyond that of the TI-990 with regards to 8-bit memory aside from the 16bit memory. My spec'd 9900 or TMS9900/10-3 (-3 for 3 mhz part) would be more equivalent to the TTL 9900 variant with the larger addressing range which is theoretically achievable with the 64 pin DIP with the handful of n.c pins. Upgradeable 16-BIT SRAM module card would have made it possible to extend that memory as upgrades allowing you to do so much more as well as upgradeable DRAM memory card slot. This would make way for some very impressive upgradeability. If we could also engineer the system in such a way that could allow the CPU to be clocked up to 6 or 12 or higher MHz when they become available. Such a system could become something far more than computers by others for years. To bad we don't have a working time machine. Their minicomputers had some interesting stuff that would be more than a decade to be common place on PCs. This was why the 990 minicomputers the CPU was made for and implementation with TTL enabling powerful operating systems like DNOS back in 1979.

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On 11/11/2022 at 11:03 PM, Wildstar said:

In 1977-1979, it would make no difference in performance considering SRAM chips, especially the 16 bit ones, were able to keep up with the CPU. Intel, in fact, borrowed a page from the TI-99/4 and 4A. Take a look at the 386 and 486. An Intel x86 processor did not directly accessed the main memory. They interfaced through a memory controller. However, it directly accessed a memory called cache memory. This would be roughly equivalent to scratch-pad memory that TI devised. This became beneficial when today's processors were too fast for system memory.

 

Back with the 386, that system memory would be DRAM because they were cheaper and provided more memory per dollar but they are slower. Current DDR5 SdRam is still a type of DRAM. SRAM would be faster but still too slow for efficient cache of L1/L2 level but was for L3 until more recently, when it was still an external chip on the motherboard. The 286/386 would not have on-die cache. It would be external SRAM. They were maybe 4k or 8k early on and increased to maybe 128kb. In 1979, 256 bytes was a sizable SRAM. If they had put 2KB or 4KB, it would have been extraordinary.

 

By 1979, they should have had 16 bit address lines for 128KB. They should have included a MMU/memory controller to allow internal or external RAM expansion of maybe 1 to 2 MB.  TI would have to upgrade to an 80 pin package by 1980/81. This would then allow the design for direct addressing more memory but the whole computer system upgraded to be able to facilitate a lot more memory than the TI-99/4A ended up being. Additionally, a full-size keyboard comparable to the IBM PC at the time. Cartridge port maybe moved to the back or facing upward. A side port could remain and PEB being a tower can (which some TI PEB owners ended up doing anyway), and include it as part of the package.

 

In this case, focus on competing with Apple II and IBM PC instead of trying to compete against Commodore so directly on the low end. Further improvement would be for TI to increase the speed to twice to four times the current speed. It would compete with 8086 and 286. Add pre-fetch and deep pipeline, and the chip can perform competitive to the 386 and 486. Eventual architecture upgrades to address the evolving market. Possibly evolving to an architecture that can switch between 16 bit and 32 bit and 64 bit. A modern 64 bit TMS 9900 with deep pipeline and on-die scratch pad memory can be incredibly fast, require a fraction of the transistors in the x86-64 chips of today and huge multi-core counts within the footprint and transistor count of a 12th generation i9. The key is to have scratch pad memory that keeps up with the cpu. Deep pipelining the bus can speed things up regarding effective clock cycles an opcode instruction requires to perform. The 6502 was already pipelines to some extent in a sense of being some kind of prefect pipeline of sorts. TI did some kind of prefect pipeline in a successor model of the TMS99XXx series.  The TMS9900 had impressive context switching because it was designed around the TI990 which was designed for multitasking. DNOS and DX10.

 

Which had they not over compromised the cpu and computer architecture, they could have potentially have a computer with networking, multitasking from their DNOS and DX10 and give it a GUI by 1979 or 1980. The video chip was duly capable. As well, they could have the genlock fully function in the consumer production. They were, after all, putting a minicomputer into a microchip. They had something that could rival an Amiga operating system, albeit on a less colorful graphic chip. With a video card in the PEB, they literally could rival Amiga and PC for years. 

 

They didn't it out as well as they could have. Imagine being able to have the scale and potential of TI-990 on a microcomputer that could serve and upgradeable for 8 to 10 years with future upgrade models that can upgrade out for 10 years introduced every 3-5 years. Same OS platform with upgrades/updates.

 

 

 

The only thing I mentioned about performance was internal registers. 
Moving registers internally would most definitely make a difference in performance as their contents can be accessed without memory cycles. 
Just break down the steps in adding one register to another.
External registers: load instruction, load register 1, add register 2 from RAM, write results back to register 1
With internal registers: load instruction, add register 2 to 1 internally
Even if there were no internal steps taking place outside of memory clock cycles, those can still take place during DMA, and the CPU would only need to halt before accessing memory again.
With pipelining, chips like the HD6303 (Hitachi's version of the Motorola 6803), register to register operations take a single clock cycle which is needed to load the opcode from RAM, and that's around 5 years before cache started appearing on CPUs.
Die sizes had to shrink a lot for cache to be practical, and that didn't happen till at around 1985.

The 9900 was originally conceived to replace discreet logic in their mini-computers.  It was supposed to access 16 bit RAM.
If by memory controller you mean the external chip that deals with addressing an 8 bit buss.  That was to make the design smaller & cheaper, but at the cost of speed.
The 9905 was supposed to be what would go into the Ti-99.  It had the 8 bit memory access built in, and several optimizations to the instructions over the 9900.
The problem with the external controller is it adds cost, increases the size of the design, and it generates more heat.
When they introduced the Ti-99 at around $1000 it wasn't an issue, but when they got into the price war they were loosing money.
It's definitely a contributing factor to why TI bailed on the personal computer market.
It you simply attach 16 bit RAM to the CPU, the board would have to be larger, but the memory controller just goes away, and the CPU runs full speed.

The 9900 had scratch memory, but it was just regular RAM attached to the CPU, so it's cache in a sense, but from software rather than hardware. 
The ROM treated it as a scratchpad to temporarily hold information because the rest of RAM had to be accessed via commands to the video chip. 
To access RAM off the 9918, you write the address you want to access, a command to read or write, and then those bytes are sent/received one at a time through the 9918. 
One of the considerations on other CPUs with a 9918 is to not try to read or write bytes too fast or the 9918 can't keep up.
Memory controllers are very different, and caching RAM accessed through the 9918 via hardware could be a rather large and complex design for the time.
The machine design was a compromise.  RAM was really expensive, and the 9918 required it's own video RAM instead of sharing RAM attached to the CPU's buss like other machines.
The machine could have been a lot faster if they had just put 4K of RAM on the CPU, allowed expansion to 32K or whatever, and used that for program storage. 
But then it would need 4K CPU RAM + 16K video RAM, which would have put it out of the home market price range.
So they came up with the idea of using video RAM for program storage, and scratchpad RAM to hold CPU registers, the BASIC interpreter's variables, etc...
If they had just designed the 9918 to share CPU RAM on alternating clock cycles with the CPU, the whole mess could have been averted.  It might have to steal some clock cycles like on the C64, but it would still be way faster.

Competing with intel is a bit of a pipedream.  The instruction set, and register setup is certainly decent when you compare to the 8086, but a whole lot has to happen to extend the design to 32 or 64 bits.
intel was adopted by IBM, the 9900 wasn't.  That alone would doom any future upgrade path for the chip.
The video chip most definitely is not capable.  It is good for games, but even then you'll notice games on MSX are usually certain types where you aren't doing a lot of full screen stuff.
The 9918 doesn't have 80 column text, completely ruling it out for professional use.  This alone would prevent it from competing with the Apple II.
The followup chips Yamaha produced added 80 columns, but those came mid 80s, and they still had memory access limitations for the CPU.
To this day, graphics cards offer a way for the CPU to directly access video RAM, something the 9918 doesn't do.
Talking about competing with the Amiga... oh man.  The thing that made the Amiga great was pretty much how it integrated everything off the memory buss.

If you want to go back in time and change things so TI competes... it's a huge can of worms. 
I won't say it couldn't have been possible, but it would have required a lot more foresight.
It's tough to know where things are going when you are in completely uncharted territory.

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There's not really any point in speculating on what the TMS 9900 should have been. It was simply a reduced chip count implementation of the TTL chip CPU implemented in the TI 990/9. That's what it was supposed to be.

It's more interesting to look at further developments, with different objectives, like the TMS 9995 and TMS 99000 versions, and then expand from there. What if they had made a single chip solution of the TI 990/12? But when they could have done that time was already running out.

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Oral history: https://www.computerhistory.org/collections/catalog/102746447
CHM Ref: X6589.2013 © 2012 Computer History Museum Page 16 of 36 
Aug 12, 2012

 

Wally Rhines: 

 

Quote

About this time [1978], another blow-up occurred in the Semiconductor Group. TI had a 16-bit microprocessor because they had missed the boat on 8-bit microprocessors. So they had done a second source of the 8080, or 8080A actually, and tried to sell it, but they were learning that you couldn’t just produce a part. You had to have application engineering support. So TI had not been very successful. Jack Carsten at that time was head of MOS, and he had under him, in addition to the second source 8080, there was a 5500 family of 8-bit processors. It didn’t do very well either. Well, it did well in some places, but didn’t become famous. But the lifesaver was going to be the 9900. 

 

[Me: Doesn't mention TI's revenue from TMS1000 and 7000 microprocessors.  For the second time here, 5500 is probably a misstatement.  Adam Osborne analyzed TI's microprocessor business at this time, in great detail. Osborne's report is in the TI Archives.] 

 

Quote

And there was a corporate strategy. This was a microprocessor that was compatible with our mini computers and terminals and our military business. One microprocessor architecture for the whole company at the 16-bit leading edge. And so the 9900 had been developed starting I guess sometime in the ‘70s. And it was struggling. Because it had a 16-bit logical address space. 

 

[Me: he must mean 16-bit bus width here.]

Quote

 

So the only people who really needed 16-bit microprocessors that would use the 9900 did it for performance or resolution, 16 bits versus 8. But in terms of performance, that was a pretty narrow niche. And so they, in trying to make a success of the strategy, (which at that time reported to Jim Van Tassel), got a young engineer, Kevin McDonough, to design a version with an 8-bit data bus. 

 

They called it the TMS 9980.  And you could use 8-bit peripherals, since the most visible problem up to that point had been no peripherals for the 16-bit microprocessors. Now we’ve got peripherals. Well, Jack Carsten had gone to Intel and he was watching what we were doing and he thought we actually knew what we were doing. And so Intel said, “Oh, my gosh. TI has got an 8-bit wide data port on their 16-bit microprocessor. Let’s put one on ours.” 

 

And there the Intel 8088 was born. And so Intel had the 8086, which they introduced in April of 1978, and TI had the 9900 which was not doing very well in the market and the 9980 not doing much better. And by then the TI microprocessor group was losing credibility and so there was a blowup and the manager was moved to another position. And the logical person to come run it was the one
who was running the successful design group in Lubbock. And of course, I <laughs> wasn’t anxious to stay in Lubbock. 


So I moved to Houston and took over the microprocessor group, which was a big responsibility for my age, but a job that no one else wanted. Because everyone knew the 9900 was not going to make it. And one of the first things I had to do was conduct exit interviews, because everyone was quitting because of another 16-bit microprocessor, a single chip micro-controller, that they couldn’t manufacture. So everybody was quitting. It was a real disaster when I arrived, but it was better than living in Lubbock.

 

 

[Me: this must refer to the TMS9985, which the 99/4A was designed around.  Karl Guttag describes the issues with the 9985, and how the 9995 replaced it.]

[Rhines then tells about the TMS320 DSP and TMS340 graphics cpu, which grew to become 40% of TI's revenue.]

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The TMS-9900 only had 16-bit addressing for a total of 64K. External chips were needed to implement memory banking if the system was to have more memory. 8086's segments may not have been much better but all the logic was internal to the CPU. 

 

That was the failure for the 9900: an expensive chip that needed expensive additional chips and logic to match the capabilities of a cheap chip. 

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What pipelining achieved in the 9995 and 99000.  When combined with its shorter memory access time & faster clock, it made the 99000 look much better, even while using external registers.  

The  pipeline in the 9995 has the same sequence, just with 8-bit external memory access, except when the registers are in the on-board 128x16-bit RAM.)

 

Move register-register: 3 cycles vs 2 on 68k or 8086.

Add registers: 4 cycles vs 2 or 3.

Move memory to memory: 5 vs 10 or 20 (what the heck is going on there?).

 

 

 

image.thumb.png.f0c8b5dfafcf1168ae5a694137554b61.png

 

 

image.thumb.png.19a26f9981ccc87613beabd38998900a.png

 

from Electronics, Feb 24, 1981. pp 156-157. "Fast on-chip memory extends 16-bit family's reach." David S. Laffitte and Karl M. Guttag, Texas Instruments Inc., Houston, Texas.

 

"on-chip memory" in the title refers not to scratch-pad RAM, (which was dropped from the 99000), but rather to the Macrostore ROM and RAM. Macrostore was code in a 2K onboard mask ROM, using 16x16-bit registers on-chip.  Macrocode comprised its own 64K logical address space (which could also be external, decoded with a simple '138.  I'm playing with this now.)  

 

External register file is an odd, but to me endearing feature.  Still, all of TI's later microprocessors used internal registers, and lots of them. 

 

 

 


Guttag's own slides on 99000 competitive benchmarks vs 8086 and 68k.  Cites external register file as a liability.  

 

 

http://spatula-city.org/~im14u2c/vdp-99xx/e1/99000_(Alpha)_Misc_Documents.pdf

 

More documents here:

 

http://spatula-city.org/~im14u2c/vdp-99xx/

 

 


 

 

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