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F18A MK2


matthew180

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Have you decided what "exactly" the daughter board options will be?  I see (in the images post, previous page,) a VGA daughter board & a TMDS daughter board.  I have to admit, that I've never heard of TMDS until now.  The research (Google search,) I've been doing seems to indicate it's an intermediary for HDMI and DVI.  The image looks like a HDMI port.  Were you able to work that out?  Or will you be shipping it without the port and letting the end user worry about that?  It doesn't look like there's enough room to put a DVI port on it, but if so, will it be DVI-D and include the audio signal?  I'm assuming HDMI will include the audio.

 

I'm sorry if I missed previous answers to these questions.  I don't remember reading anything about them, but I might have missed some posts, and I might just not be remembering.

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  • 1 month later...

I am allergic to certain 4-letter acronyms, so I choose to stick with the technical terms.  TMDS (transition minimized differential signaling) is similar to LVDS (low-voltage differential signaling) and is the physical layer used to transmit high-speed data in some video systems like DVI.

 

Since I have moved to having a header board for the MK2, I have designed it in such a way that it will support a VGA header and a DVI-compatable (TMDS) header.  This part is working and I have tested both headers, but I still have one revision to build and test.

 

I have also firmed up the TMDS core, so the last bit is reworking some of the older bits of HDL to decouple the video clock from various internals.  I have to do this because the digital video timing is different than VGA, and my original HDL was always evolving in quality as I learned more and got better working the HDL and FPGAs.  This is really the main piece holding up the works, but I'm finally getting some time to put some serious effort back into it.

 

Fingers crossed I can get it done soon.  Believe me when I say I want this done as badly as everyone else, and I feel really bad about how long it has taken.

 

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  • 4 weeks later...

I'm curious, when Gary Bowser made the TIM (TI Image Maker) he also made the AIM (Adam Image Maker) - in the advertisement for AIM, it was mentioned CPM for the ADAM had been extended to 80-Columns. Any TIer familiar with the Adam, know if there is a bunch of 80-column software already done for the AIM - that would run on the MKII?

 

 

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  • 2 weeks later...

This thread is so long, your question is probably not getting the attention it needs.  You should make a new thread for the question, and maybe ask in the CV subforum where there are more ADAM users.  The F18A is "T80 ready" out of the box, so if there is software for the ADAM that used the 9938/58 settings for T80, it will mostly "just work" unless the software relies on the VRAM over 16K that typically came along with the 9938/58.  The MK2 should resolve the VRAM issue.

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  • 4 weeks later...

Even if I had finished by this time last year, due to the chip shortage I cannot get a large majority of the parts, especially the FPGA, used on the MK2 right now.  So I could not get them made for the last 8 months even if I was done. :(

 

Hopefully me finishing the MK2 will coincide with parts being available.

 

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  • 1 month later...

I'm using the parts shortage as an excuse as to why the MK2 is not done yet. :P

 

Progress is slow, but happening.  Lots of pieces to bring together.  I dug myself a nice hole of requirements this time for sure.  Supporting USB updating has certainly added an amount of complexity to the project.

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On 10/16/2021 at 8:10 PM, matthew180 said:

I'm using the parts shortage as an excuse as to why the MK2 is not done yet. :P

 

Progress is slow, but happening.  Lots of pieces to bring together.  I dug myself a nice hole of requirements this time for sure.  Supporting USB updating has certainly added an amount of complexity to the project.

A truly amazing work!

 

But, excuse me Matthew, if I request an update of all the specs for the F18A MK2. I've seen lately that you added some new features to the design.

 

Could you, please, do a small resume of all the features?

 

Thanks in advance!

 

I'm looking forward this great addon!! :-D

 

 

Edited by FCastellanos
correct typos
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The primary design goals for the MK2 are:

 

* Same size as the 40-pin footprint of the original IC.  Removes the physical problems of installing in different systems. (done)

* Digital video output, and now also supports VGA output (requires a firmware change). (done)

* 512K of VRAM, with support for placing VDP tables anywhere in the VRAM. (physical SRAM is done, updating HDL to support external SRAM is WIP)

* Built-in firmware updating via USB to a PC. (proven, WIP)

* Audio capability via 12-DAC, also includes 12-bit ADC to sample the host-system audio which allows mixing and control (requires external connection of host audio signal). (done)

* Compatible with original F18A. (WIP, ongoing as HDL is written)

 

Anything other enhancements are not designed yet and would be available via a firmware update.

 

One of the tasks that make things slow-going are decoupling the F18A core from the video scan out.  When I designed the origin HDL I was learning a lot of things at the same time, and the design was very tightly bound to the video output.  Without decoupling the core, I cannot provide the digital video output, or *properly* fix a long standing timing bug in the original design (due to my ignorance while I was making the original core).

 

The USB part is a PITA too, but I swore I would not make another FPGA device that could not be updated via USB.  This requires PC software to be written, as well as support on the FPGA and other mucky bits in the middle.  It is also the only part of the design that will use HDL that is not mine (I really don't want to write a USB core).

 

The last part is some sorely needed documentation, and all the other details involved with making a product that is ready to be purchased.

 

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2 hours ago, matthew180 said:

Without decoupling the core, I cannot provide the digital video output, or *properly* fix a long standing timing bug in the original design (due to my ignorance while I was making the original core).

Just curious, am I correct in assuming that the long standing timing bug in the original design is not fixable with a firmware update?

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On 10/16/2021 at 2:10 PM, matthew180 said:

I'm using the parts shortage as an excuse as to why the MK2 is not done yet. :P

 

Progress is slow, but happening.  Lots of pieces to bring together.  I dug myself a nice hole of requirements this time for sure.  Supporting USB updating has certainly added an amount of complexity to the project.

I feel ya on the parts shortage.  It finally hit here a couple of months ago.  Also, the cost on some components has more than quadrupled over the past 8 to 10 months.  Hopefully it'll level off sometime next Spring or Summer. ?

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2 hours ago, Ikrananka said:

Just curious, am I correct in assuming that the long standing timing bug in the original design is not fixable with a firmware update?

It was "fixed" in the V1.9 firmware, but I'm not happy with the solution, and it makes things even worse for decoupling the video to support digital video.

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  • 1 month later...

Posting here, too, just for completeness.

 

I shared the project on OSHpark so you can order the board.  You will also need a 40-pin socket and the PCB pins.

 

https://oshpark.com/shared_projects/LRw0l4ER

 

PCB PINS, Mill-Max: 3157-0-00-15-00-00-03-0 Press Fit, Qty: 23, DigiKey: ED90328-ND

https://www.digikey.com/en/products/detail/mill-max-manufacturing-corp/3157-0-00-15-00-00-03-0/437069

or

Tall PCB PINS, Mill-Max: 342-10-164-00-591000 SIP header, break away 64-pins, Qty: 1, DigiKey: 575-641591

https://www.digikey.com/en/products/detail/mill-max-manufacturing-corp/342-10-164-00-591000/357033

 

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On 10/26/2021 at 7:54 PM, matthew180 said:

The USB part is a PITA too, but I swore I would not make another FPGA device that could not be updated via USB.  This requires PC software to be written, as well as support on the FPGA and other mucky bits in the middle.  It is also the only part of the design that will use HDL that is not mine (I really don't want to write a USB core).

 

The last part is some sorely needed documentation, and all the other details involved with making a product that is ready to be purchased.

 

Will there be Linux support for programming it via USB?  I don't have any Windows machines in my house.  Depending on the cost and performance, I might need a bunch to upgrade several machines.  I have three TI 99/4As, two ColecoVisions and a brother with a ColecoVision I gifted him... not sure how many I want to upgrade, but at first I might at least get two to try one out in a TI and a ColecoVision.

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