MARIA Chip Schematics Released

[Curt Vendel]

Big Announcement... I've received several requests from people working on the MIST FPGA project if they could have access to the chip schematics to the 7800 MARIA chip.

 

I have just posted all of the sheets up for the TIA-MARIA-STEPHANIE chip. Now a word of caution, there is a memory hole error in these schematics, so if anyone plans to do some VHDL and/or Verilog work please keep this in mind.

 

These sheets span work from 1983 all the way up into August 1984.

 

The link is posted on the Left Side menu in the Atari 7800 page:

 

http://www.atarimuseum.com/videogames/consoles/7800/7800menu/

[TailChao]

This is excellent info, thanks a ton!

[down3db]

On 10/19/2019 at 9:44 AM, Curt Vendel said:

Big Announcement... I've received several requests from people working on the MIST FPGA project if they could have access to the chip schematics to the 7800 MARIA chip.

 

I have just posted all of the sheets up for the TIA-MARIA-STEPHANIE chip. Now a word of caution, there is a memory hole error in these schematics, so if anyone plans to do some VHDL and/or Verilog work please keep this in mind.

 

These sheets span work from 1983 all the way up into August 1984.

 

The link is posted on the Left Side menu in the Atari 7800 page:

 

http://www.atarimuseum.com/videogames/consoles/7800/7800menu/

So I thought it might be a simple translation to VHDL, but it looks like something else is going on - perhaps some kind of current steering logic or something?

I see this and it just looks like, "Short power to ground here" - not that useful.

 

Can someone clue me in on what exactly this node is supposed to do?

 

[TailChao]

On 11/1/2019 at 12:31 AM, down3db said:

So I thought it might be a simple translation to VHDL, but it looks like something else is going on - perhaps some kind of current steering logic or something?

I see this and it just looks like, "Short power to ground here" - not that useful.

 

Can someone clue me in on what exactly this node is supposed to do?

My assumption has been the half-filled bubbles ( ◒ ) are transmission gates, so it does look like a current steer controlled by 1A5-1... and the mess that feeds into. But this is all part of the TIA's logic, Maria's drawing seems much more straightforward.

 

Started reading through some of the matrices to try and get definitive numbers out of them.

Here's the one from Maria's HORIZONTAL SYNC TIMING page.

  H H   H H   H H   H H   H H   H H   H H   H H   H H
  8 8 | 7 7 | 6 6 | 5 5 | 4 4 | 3 3 | 2 2 | 1 1 | 0 0
    B |   B |   B |   B |   B |   B |   B |   B |   B
 -----|-----|-----|-----|-----|-----|-----|-----|-----
    o |   o |   o | o   | o   | o   |   o | o   | o    HRESET
    o |   o | o   | o   |   o |   o |   o | o   |   o  HBORDERS
  o   | o   |   o | o   |   o |   o |   o | o   |   o  HBORDERR
    o |   o | o   |   o |   o |   o | o   | o   | o    HBLANKS
  o   | o   |   o | o   | o   | o   |   o | o   | o    HBLANKR
  o   | o   | o   | o   | o   | o   | o   | o   | o    HSYNCS
  o   | o   |   o | o   | o   | o   | o   |   o | o    HSYNCR
    o |   o | o   | o   |   o |   o |   o | o   | o    HLRC
    o |   o | o   |   o | o   | o   | o   |   o | o    HRPRST
  o   | o   | o   |   o | o   | o   |   o |   o | o    HCBURSTS
  o   | o   | o   |   o |   o |   o | o   | o   | o    HCBURSTR
      |     |     |     |     |   o | o   |   o |   o  HELRR


           8 7 6 5 4 3 2 1 0
           -----------------
 HRESET    1 1 1 0 0 0 1 0 0 : 452
 HBORDERS  1 1 0 0 1 1 1 0 1 : 413
 HBORDERR  0 0 1 0 1 1 1 0 1 :  93
 HBLANKS   1 1 0 1 1 1 0 0 0 : 440
 HBLANKR   0 0 1 0 0 0 1 0 0 :  68
 HSYNCS    0 0 0 0 0 0 0 0 0 :   0
 HSYNCR    0 0 1 0 0 0 0 1 0 :  66
 HLRC      1 1 0 0 1 1 1 0 0 : 412
 HRPRST    1 1 0 1 0 0 0 1 0 : 418
 HCBURSTS  0 0 0 1 0 0 1 1 0 :  38
 HCBURSTR  0 0 0 1 1 1 0 0 0 :  56
 HELRR     x x x x x 1 0 1 1 : /16 @ 11

 

[TailChao]

...and here's the line counter in VERTICAL SYNC TIMING AND RSYNC.

  V V   V V   V V   V V   V V   V V   V V   V V   V V
  8 8 | 7 7 | 6 6 | 5 5 | 4 4 | 3 3 | 2 2 | 1 1 | 0 0
    B |   B |   B |   B |   B |   B |   B |   B |   B
 -----|-----|-----|-----|-----|-----|-----|-----|-----
    o | o   | o   | o   | o   | o   |   o |   o | o    VRESET
  o   | o   | o   | o   | o   | o   | o   |   o |   o  VSYNCR
  o   | o   | o   | o   | o   | o   | o   | o   | o    VSYNCS
  o   | o   | o   | o   |   o | o   | o   | o   | o    VBLANKR
    o | o   | o   | o   | o   | o   | o   |   o | o    VBLANKS


           8 7 6 5 4 3 2 1 0
           -----------------
 VRESET    1 0 0 0 0 0 1 1 0 : 262
 VSYNCR    0 0 0 0 0 0 0 1 1 :   3
 VSYNCS    0 0 0 0 0 0 0 0 0 :   0
 VBLANKR   0 0 0 0 1 0 0 0 0 :  16
 VBLANKS   1 0 0 0 0 0 0 1 0 : 258

 

As above - these are just the matrices' contents, and does not include their attached logic. So the discrepancies between what's here and what's been observed in the actual chip's timing may be caused by this.

[Geoff Oltmans]

Maybe depletion mode transistors?

[down3db]

2 hours ago, Geoff Oltmans said:

depletion mode transistors?

 

On 11/2/2019 at 9:46 AM, TailChao said:

My assumption has been the half-filled bubbles ( ◒ ) are transmission gates, so it does look like a current steer controlled by 1A5-1... and the mess that feeds into. But this is all part of the TIA's logic, Maria's drawing seems much more straightforward.

 

Started reading through some of the matrices to try and get definitive numbers out of them.

Here's the one from Maria's HORIZONTAL SYNC TIMING page.

  H H   H H   H H   H H   H H   H H   H H   H H   H H
  8 8 | 7 7 | 6 6 | 5 5 | 4 4 | 3 3 | 2 2 | 1 1 | 0 0
    B |   B |   B |   B |   B |   B |   B |   B |   B
 -----|-----|-----|-----|-----|-----|-----|-----|-----
    o |   o |   o | o   | o   | o   |   o | o   | o    HRESET
    o |   o | o   | o   |   o |   o |   o | o   |   o  HBORDERS
  o   | o   |   o | o   |   o |   o |   o | o   |   o  HBORDERR
    o |   o | o   |   o |   o |   o | o   | o   | o    HBLANKS
  o   | o   |   o | o   | o   | o   |   o | o   | o    HBLANKR
  o   | o   | o   | o   | o   | o   | o   | o   | o    HSYNCS
  o   | o   |   o | o   | o   | o   | o   |   o | o    HSYNCR
    o |   o | o   | o   |   o |   o |   o | o   | o    HLRC
    o |   o | o   |   o | o   | o   | o   |   o | o    HRPRST
  o   | o   | o   |   o | o   | o   |   o |   o | o    HCBURSTS
  o   | o   | o   |   o |   o |   o | o   | o   | o    HCBURSTR
      |     |     |     |     |   o | o   |   o |   o  HELRR


           8 7 6 5 4 3 2 1 0
           -----------------
 HRESET    1 1 1 0 0 0 1 0 0 : 452
 HBORDERS  1 1 0 0 1 1 1 0 1 : 413
 HBORDERR  0 0 1 0 1 1 1 0 1 :  93
 HBLANKS   1 1 0 1 1 1 0 0 0 : 440
 HBLANKR   0 0 1 0 0 0 1 0 0 :  68
 HSYNCS    0 0 0 0 0 0 0 0 0 :   0
 HSYNCR    0 0 1 0 0 0 0 1 0 :  66
 HLRC      1 1 0 0 1 1 1 0 0 : 412
 HRPRST    1 1 0 1 0 0 0 1 0 : 418
 HCBURSTS  0 0 0 1 0 0 1 1 0 :  38
 HCBURSTR  0 0 0 1 1 1 0 0 0 :  56
 HELRR     x x x x x 1 0 1 1 : /16 @ 11

 

The half filled bubbles make sense as transmission gates. 

Do we have a timing diagram for this chip somewhere? 

 

 

[TailChao]

9 hours ago, down3db said:

Do we have a timing diagram for this chip somewhere?

There's various captures scattered around the forum, but unfortunately no definitive set.

 

Doing full captures of Maria's render activity has been on my todo list, but I'm not sure when I'll be able to come back to it. I think @kevtris was also working on this some time ago.

[down3db]

1 hour ago, TailChao said:

There's various captures scattered around the forum, but unfortunately no definitive set.

 

Doing full captures of Maria's render activity has been on my todo list, but I'm not sure when I'll be able to come back to it. I think @kevtris was also working on this some time ago.

I think I'm going to begin the attack by looking at Maria's "reset" line. I found a paper on implementing a TGate in VHDL (obviously, a behavioral model), but it will allow us to simulate. There are a few other things I don't understand about the schematic (...a number of them, really) but hopefully as a group we can figure it out?

 

I'm trying to blow the schematic up and then re-draw sections of it with LibreOffice Draw or Inkscape, so we can cut/paste portions of the schematics and mark it up as we go along. Kind of a PITA, and slow going, but hopefully it will be helpful. 

[down3db]

Are these transmission gates also inverting the signal as it is passed? That's the only way I can make sense of this. 

 

 

[kevtris]

I didn't do capture on it, but I did use the schematics to implement it in verilog awhile back for an FPGA 7800 core.

[ChildOfCv]

10 hours ago, down3db said:

Are these transmission gates also inverting the signal as it is passed? That's the only way I can make sense of this. 

 

 

I don't see how one could (unless another power connection is not shown).

 

The fact that it says RAMCELL there, though, suggests that maybe this is a DRAM bit?  If so, they work as capacitors and not as flip-flops.  That's why they need constant refresh.  A read is destructive since it depletes the charge, so there is a constant counter that goes down the line reading and rewriting each row of RAM.  A gate has a certain level of capacitance, and it is possible that they are using it as a feature, much like they do with the shift register for color output.

[+bsteux]

Hi,

The link to atarimuseum to get the schematics is not working anymore. Would anyone still have its own copy of the Maria schematics ? I'm a former teacher of VHDL and I was wondering if I could be of any help working on a Maria ASIC remake.

Best regards.

[+Stephen Moss]

I don't know if this is what you are after but I have a PDF that appears to be for Tia-Maria-Stephanie or is it was something else you were looking for.

You should be able to download it from here 

 

 

[+batari]

On 11/5/2019 at 12:25 PM, down3db said:

Are these transmission gates also inverting the signal as it is passed? That's the only way I can make sense of this. 

 

 

 

On 11/5/2019 at 11:27 PM, ChildOfCv said:

I don't see how one could (unless another power connection is not shown).

 

The fact that it says RAMCELL there, though, suggests that maybe this is a DRAM bit?  If so, they work as capacitors and not as flip-flops.  That's why they need constant refresh.  A read is destructive since it depletes the charge, so there is a constant counter that goes down the line reading and rewriting each row of RAM.  A gate has a certain level of capacitance, and it is possible that they are using it as a feature, much like they do with the shift register for color output.

Old post.. but, this is just a standard 6-transistor SRAM cell. Here is a better illustration:

 

[ChildOfCv]

2 hours ago, batari said:

Old post.. but, this is just a standard 6-transistor SRAM cell. Here is a better illustration:

Hmmm.  But in the original diagram, it looks like M3 and M4's gates are connected to their own drains, not to their counterpart gates/opposite Q's.

 

Also, it appears that both input and output are interchangeable.  Is that an accurate observation?

[+batari]

7 hours ago, ChildOfCv said:

Hmmm.  But in the original diagram, it looks like M3 and M4's gates are connected to their own drains, not to their counterpart gates/opposite Q's.

 

Also, it appears that both input and output are interchangeable.  Is that an accurate observation?

Well, maybe the diagram I posted isn't the exact representation, but when I first saw this I immediately thought, this is clearly a 6-transistor SRAM cell, as it's very common thing. But as you noticed, there are other ways to accomplish this. The basic idea is this:

 

 

Normally I think the inverter piece essentially looks like this:

 

But, another way is like this:

 

You can make a resistor (albeit kind of a crappy one) by tying gate to drain in an enhancement mode mosfet:

So I

So that is my thought on what they did here.

[+bsteux]

On 2/27/2023 at 9:33 AM, Stephen Moss said:

I don't know if this is what you are after but I have a PDF that appears to be for Tia-Maria-Stephanie or is it was something else you were looking for.

You should be able to download it from here 

 

 

Thanks! This is what I was looking for.