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# Horiztonal Movement Code Question

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I'm having a challenge understanding the divide portion of this code.

```        LDA PlayerXPos
AND #\$7F

STA WSYNC
STA HMCLR

SEC
DivideLoop:
SBC #15
BCS DivideLoop

EOR #7
ASL
ASL
ASL
ASL
STA HMP0
STA RESP0
STA WSYNC
STA HMOVE```

The video I watched stated that you wanted the remainder for the "fine" positioning, which I believe is -8 to +7.  If I use the value 20 for PlayerXPos, I expect a remainder of 5, as 15 goes into 20 one time with a remainder of 5.  After doing the exclusive or, and the four left shifts, I end up with the value 0001 for the upper 4 bits, not five.  If I worked from 30, and subtract 10 to arrive at 20, then that's out bounds of the negative range, thus it would have to be 15 + the remainder 5.

I don't yet know why the one's complement is taken of the lower three bits, nor where my thinking is flawed, but it's flawed alright.

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Let's have a closer look at what's happening here, until the internal counter position for player 0 is actually latched in the TIA.

First, mind that for a value of 20 we're not just subtracting 15 once with a remainder of 5, since the remainder will be still positive, hence the carry is still set and SBC will branch. Only after the next subtraction, we'll end up with a value less than zero (-10) and proceed with the EOR.

At this point (after the last subtraction) the accumulator is \$F6 (-10), but we're actually concerned with the lower 4 bits only (since the higher ones will be shifted out). After the EOR, the accumulator holds \$F1, or, after the shifts, a \$10, which corresponds to a HMOVE offset of +1.

Hum. Still not what we may have expected.

Let's have a look at the cycle count, right after the CPU restarts after WSYNC:

```STA zeropage  (3)  3
SEC           (2)  5
SBC immediate (2)  7
BCS branching (3) 10
SBC immediate (2) 12
BCS no branch (2) 14
EOR immediate (2) 16
ASL           (2) 18
ASL           (2) 20
ASL           (2) 22
ASL           (2) 24
STA zeropage  (3) 27
STA zeropage  (3) 30
--------------------
30 CPU cycles = 90 color clocks
AC = \$10 => HMOVE offset +1```

After 90 color clocks, we're 22 pixels into the playfield (since HBLANK lasts for 68 color clocks).

An offset to the left of +1 (HMOVE) will give us 21, which is still a pixel off, at least in my calculations.

Still, we're missing some. The signal is actually set on the data bus during the third CPU cycle of the STA instruction, which may account for the difference. On the other hand, it'll take a bit until the signal is actually latched in the TIA. (From a CPU perspective, we're dealing here with a bit of a Heisenberg blur. But, given that a CPU cycle has actually two phases, one where the R/W signal is low and the CPU is writing to the bus, followed by a second phase, where the R/W goes high and the CPU reads from the bus, we may conclude that the write occurs during the first half of the third CPU cycle, when the color clock is closer to 20 or 21 than to 22.)

Edited by NoLand
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Well, NoLand, that was fantastic.  I wish I would have explored the clocks, I thought about it, but I was hunting a five and let the opportunity pass.  Much appreciated NoLand.

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This is in the 6502 Hardware manual, http://www.bitsavers.org/components/mosTechnology/6500-10A_MCS6500hwMan_Jan76.pdf

What I do not really know, is how long the TIA takes to latch the signal. I recall somewhat faintly that it may be as much as 2 TIA clocks. But I wouldn't even know where to look this up.

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11 minutes ago, NoLand said:

This is in the 6502 Hardware manual, http://www.bitsavers.org/components/mosTechnology/6500-10A_MCS6500hwMan_Jan76.pdf

What I do not really know, is how long the TIA takes to latch the signal. I recall somewhat faintly that it may be as much as 2 TIA clocks. But I wouldn't even know where to look this up.

Thanks for the manual link NoLand.  I just recently bought Lance Leventhal's 6502 book on ebay, but I'm not too far in yet.

Regarding the latch, in the atari course I'm taking, I don't recall that being mentioned yet thus I have no idea of it's importance at this time.

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There are some pretty competent folks here on AtariAge, who are actually exploring the TIA and are coding emulations. Maybe, one of them may drop in with some details.

Also, regarding manuals, there's also some detail in the 6502 Programming Manual, http://www.bitsavers.org/components/mosTechnology/6500-50A_MCS6500pgmManJan76.pdf

There's detailed information on what happens during each CPU cycle, but not much on what's happening below the cycle level.

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OK, regarding 650x timing and when the write actually occurs, if I'm interpreting the following diagram right, it's only near the end of the third CPU cycle.

The diagram should match the third cycle (T2) in STA zeropage, on the address bus is 00, ADL (hi, low address) and the data to write is on the data bus with R/W going low. According to this, the data is put on the bus just before the middle of the second phase of a cycle, which should be about a TIA color clock before the end of the CPU cycle. (This wouldn't allow for much of another delay to occur on the TIA's side. Or, if there is a delay for the signal to become effective it would have to be compensated internally for accurate counter values.)

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