matthew180 Posted August 12, 2021 Share Posted August 12, 2021 The SPI flash needs to be 1MB (8Mb) and 100MHz or better, since assumptions are made in the firmware about access speed and size. It also needs to match the footprint. Other than that, it can be larger in capacity. As for the shorts between FPGA pins, there are a lot of design changes I would make if I reworked that board. One of them being that I learned a lot about routing, and I will never connect adjacent pins on the FPGA directly. I have reused a single FPGA multiple times, but rework is easily 2x harder than soldering, and heat definitely kills components and damages the PCB. It is easy to get too much solder on the FPGA pads and have solder bridges behind the legs. Even harder to clean the flux back there so you can see. The only way to clean it all seems to be the ultrasonic cleaner. On 8/10/2021 at 5:55 PM, WicoKid said: If anyone has a board out can you verify continuity or not between positive C18 and negative C8 after FPGA placed. The resistance between C8 and C18, on the FPGA-side, is about 400-ohms through the FPGA. None of the caps should be shorted to ground on the FPGA-side (the other side *is* ground). 3 Quote Link to comment Share on other sites More sharing options...
Join the conversation
You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.