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1090XL remake


kenames99

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On 10/10/2021 at 10:26 PM, kenames99 said:

hi,

  I just finished putting the 80 column card into kicad. here is a pic generated by kicad. Some components changed, like the video out jack and rotary switch, no current replacements available. I would like to know if there is any interest in this or any of the 1090XL and associated boards to go with it. this represents quite a few hours of time for each board so I would like to know if this is a waste of my time. I know some have said they want to see these, like post #2 in this topic, along with some others. and I appreciate your support. I am going to order 5 boards to test design and operation. I will likely keep 2 and will sell the other 3 most likely as bare boards.

 

Ken

 

80cvc.jpg

What video chip does this upgrade use?  Is it monochrome or does it support colour?

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On 3/14/2021 at 9:30 PM, kenames99 said:

hi,

  A while ago, before Curt Vendel passed away, we were colloberating on a reproduction of to 1090xl expansion box. I was remaking the board and Curt was going to do the mechanicals parts. I do not know how far he got but I got the board design done. I never had the chance to get it produced. would there be any interest for me to put this on a github repo?

 

thanks

Ken

 

1090XL.jpg

For what it's worth, when I was over there last month beginning to catalog everything he had a 1090 and related documents on his desk (next to his XM project area). Now I know why that was there.

 

 

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hi Retro Rogue,

  wow, sounds very cool indeed! hope you had fun and got a lots accomplished, what a task tho. been having fun with this whole project, am currently working on the 80 column board. currently not working so gotta find what I did wrong. would you be able to provide some hi res pictures?

 

  did you ever get the atari museum site back online? I am really looking forward to that.

 

  also, a quick note for everyone, dont use the linear regulator on the ram board! put in a switching regulator instead, TPSM84205 should do a good job - available thru most sellers, and do not install the 22 ohm 2 watt resistor. I had a voltage surge here and it killed my ram board.

 

   Good to see you around here.

 

Ken

 

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54 minutes ago, kenames99 said:

hi,

  I just updated my github. small correction on 50 pin edgecard size.

 

  Also, just wondering, does anyone have any plans to produce plugin boards or the 1090XL board?

 

thanks.

Ken

 

I think a 4MB memory card could be made quickly.  My belief is that bank selection could be done via the PBI registers by having the right logic in the parallel device at some address from $D100 to $D1FF.  If I am right, banking could be done Axlon style but with the banking set at $D100.  The Atari's internal memory would have to be disabled by setting PB_EXTSEL low.  But there would need to be software to support it.  If there's interest, I'll figure out the details.  (Of course, feel free to let me know if I have this completely wrong....lol)

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3 minutes ago, kenames99 said:

hi reifsnyderb,

  memory or almost anything in the pbi can be handled independent of anything inside atari unless the internal atari mods interfere in the D1xx, D6xx, od D7xx memory areas. so, no reason why that would not work, driving software/handler would be put in the D800-DFFF memory area reserved for it.

 

Ken

 

Would a driver even be needed?  I am not sure as most of the parallel port articles are lacking.  I did look over the 600 XL's memory upgrade and it looks like it just disables the internal memory and takes over.  It doesn't have banking, though.  The thing that concerns me is the D100-D1FF region, while reserved for PBI devices, could have conflicts with other PBI devices.  Do you have any documentation (other than the Earl Rice series of articles) that gives a better description?  (Or point me in the right direction to the documentation.)

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pbi devices are supposed to follow an id convention to avoid stepping on other items, the black box steals them all but the MIO does not... so... it's in the specs and all of that was here there and everywhere littered around in the threads over the years.

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22 minutes ago, _The Doctor__ said:

pbi devices are supposed to follow an id convention to avoid stepping on other items, the black box steals them all but the MIO does not... so... it's in the specs and all of that was here there and everywhere littered around in the threads over the years.

It sounds like such a memory device should completely take over the memory and have some sort of device driver and/or id convention to change banks then.

 

Found some more info in Mapping the Atari:

 

D100-D1FE -- Device Registers

D1FF  Hardware select register.

Edited by reifsnyderb
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6 hours ago, kenames99 said:

is that the full document with all 3 revisions in it?

It is, yes.  It's on the 22nd page. 

 

There is a conflict on D1FE with something called the S-16 on page 26 and I am not sure what to make of it because the description on page 26 doesn't seem to match what the 1090 schematic is nor match the pinout of the parallel bus.  So I think it's safe to use the 22nd page and assume the S-16 description is unrelated.

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It's interesting that the 10/14/83 revision talks about the expansion box now being a smart device with its own CPU so it can be used with the 400/800.  The 5/11/84 revision is back to the PBI version.  The PBI Specs that start on my page 22, section 1.0 again, are from an earlier revision of the document.  I'm trying to find the orignals.

 

Enclosed here is the 5/11/84 scan from the Museum. 

1090_hardware_tech_spec-11MAY84.pdf

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35 minutes ago, kheller2 said:

It's interesting that the 10/14/83 revision talks about the expansion box now being a smart device with its own CPU so it can be used with the 400/800.  The 5/11/84 revision is back to the PBI version.  The PBI Specs that start on my page 22, section 1.0 again, are from an earlier revision of the document.  I'm trying to find the orignals.

 

Enclosed here is the 5/11/84 scan from the Museum. 

1090_hardware_tech_spec-11MAY84.pdf 835.05 kB · 1 download

Thanks!  That answers my question about how each expansion board knows it's device id.  The device id should be set on the board.  Each board then needs to have a way to have it's device id set (jumpers?  DIP switches?  Rotary switch?) and have the logic to respond to that device id.  If that concept is followed to it's logical conclusion, and 4 MB memory boards are created, then banking would be done as follows:

 

1.  Set the board ID in D1FF.

2.  Set the bank in D1FE.

 

20 MBs of RAM would be accessible if all 5 boards are used.

 

(Admittedly, there is some discussion about how banking was planned differently in D1FE.  But since those memory boards do not appear to exist I think it's safe to use the entire D1FE byte to set the bank.)

 

I have been looking for memory to use for such a board.  Unfortunately, the cheaper options are BGA and they have their own challenges to board design and soldering.  If the same memory is used that I used on the 600XLM, each MB is over $8.00 for the chip.  So a 4MB board has around $35 in just memory chips.  

 

Edit:  Changed number of boards to 5 and total RAM to 20.  Originally I was thinking 8 boards because there are 8 id's and forgot there 5 boards with 8 possible id's.

 

Edit again:  After thinking more about this, there would have to be a board that would handle the main, lower, 64k.  The other boards would conflict unless a single board could be set "active".  So, it would be safest and easiest to keep the limit to 1 board only and just use D1FE to control the bank.  But with the proper logic I think it would be possible to have up to 5 boards...just any conflicts would have to be avoided.  At this point, having 1 4MB board would be good.

 

Edited by reifsnyderb
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