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FarmerPotato

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Today:


More microcode. The are preliminary, loose leaf copies of 3 TMS7000 books for microcoding.  
 

TMS7000 Micro-architecture

TMS7000 Microcode Development Users Guide

TMS7000 Micro Assembler 

 

Only the first is at Bitsavers or https://electrickery.nl/comp/tms7k/

 

I scanned much of the other two. I did not have the time to scan this real prize: the full definitions file to the Tms7000. Fully commented, how every instruction is implemented.   Which you would need as a starting base, if you were making a custom CROM (CROM is where the microcode exists in the CPU. Make your Conan the Barbarian jokes!)  Customers were allowed to replace the "non core" instructions with their own. 
 

There is a description of the hardware bench test which Texas Instruments would used on your custom 7000. Or any 7000 hot off the die. (I dunno if they actually get hot, but it sounds cool.) 

 

Finished scanning the MDS-990 book. Microcode development for the 990/12.   The MICASM definitions file for 990 led me to hope it would give source code for the 9900 instruction set. Like the TMS7000 flavor does! Alas, it defines only the equates and macros that you need. 
 

Colin Hinson used MICASM to create a custom CPU for teletext. It was a versatile tool.  
 

There were two draft specs for TMS32010 and 32020.  These also describe the internal buses and units inside the chip, but it seems a bit preliminary.  No microcode.
 

I didn't come across any more Home Computer or TIPC mentions today.  Nor any sign of more 990 manuals beyond the known cache of 1000. 

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Teletext
 

Two folders on NAPLPS and Videotex/Teletext. NA is North American.
 

First folder compares features of NAPLPS to 4 kinds of Videotex or Teletext.  There's a plan to distribute an EVM board using 9118/9128 and 9995. It's all out of Houston.

 

I'm not aware of NAPLPS  ever being deployed.  And nobody writing in this folder makes any reference that TI Bedford UK designed and sold Teletext chips used around the world.  I assumed they would factor that in somehow--nope. 

 

Colin  is the person to go to for Teletext.

 

The second folder is the NAPLPS standard. Nobody from TI is listed on the committees! 

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Posted (edited)

NuMachine, 1983
 

Texas Instruments would buy NuMachine, to make their own graphics workstations.  

 

I pulled the NuMachine folder.  It starts with a 3-page memo from Wally Rhines, who rapidly lists all the reasons why NuMachine is future-proof.  Wally is the guy who took over Microprocessor and then Semiconductor around 1982. He wanted 32-bit machines. (And especially to bury the 9900.) 
 

Beyond that, the folder was disappointing.  Every manager gave slides on how NuMachine might fit into their business, or not. A lot of castles in the clouds. Near the end, I looked at what the Design Automation Department thought they could do with it. DAD was already invested in Apollo workstations for IC designers, which integrated with their software on 990s and IBM mainframes. 
 

Others know the rest of the story better than me.  We got Explorer as TI's LISP machine, and NuMachine appeared as SB1500 with TI Unix (AT&T SVR3.2).   Dunno how long before they killed the idea of an engineering workstation.  

 

Wally Rhines went on to be CEO of Mentor Graphics. 
 

NuBus got an IEEE standard, spearheaded by TI.  Apple adopted NuBus for Macintosh II,  NeXT adopted NuBus  too. TI made a family of NuBus controller chips like ACT2441, which I've only seen in one NuBus card ever.  You could make an 8-bit NuBus card with ordinary TTL and a few PALs. (The ALS561 registered transceiver was key, and that function is long obsolete.)   See 1990 Nubus Interface Products at Bitsavers.

 

There's one more little Explorer folder that I didn't have time to get to. 

 

EDIT:   I found TI Technical Journal, Artificial Intelligence special issue, from 1987.   It has articles on Explorer, and Compact Lisp Machine, a one-chip VLSI Explorer on a NuBus. 

Edited by FarmerPotato
TI Technical Journal
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1975 Consumer and Games chips 
 

I saw the 1975 "Consumer Circuits" data book.  This includes all the SN76 series of chips. One chapter covers all of their "Pong" and TV game chips.  Also the 76477 sound generator.  Other chips were "Automatic English generator" (when your ball bounces off the paddle.) Obstacle/Wall generator. Integrated Game Logic (built-in English!)  Cute drawings of big-pixel  graphics you could get from  the character generator chips: Flapping bird (2 frame animation!), SpaceWar ship and explosion, weird looking humanoid athlete. 

 

There's a thread somewhere here about all those.  These chips soon vanished from the catalog, except for the 76477 "Sound Gizmo".  Later came the 76489 sound chip we all know. Must be the only thing in the SN76 games chips that made it big.


The bulk of the Consumer catalog is chips for broadcast analog television, telephones, calculators and clock-radios. 


I found the 4-bit Microwave Oven chip databook! The TMS1976, and TMS1117 Capacitive Touch Keypad chip that works with it! Part of the TMS1000 family.  These stuck around in the catalog for 10 years! 

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The Alpha  
 

I read the draft Functional Specification.  At first, it seemed like a mostly polished draft of the TMS99105/110 data book, aka Alpha. But then extra things, weird things, unimplemented things, stuck out. It's the functional spec and data sheet for the 99000, the CPU of the 990/10A. 

One: it documents the LMF instruction for the 990 memory mapping. This is supposed to quickly copy 16 words of the source operand to CRU word-I/O addresses.  The table is missing in the back of the book: LMF will write Map 0 starting at CRU 9FC0, Map 1 at 9FE0.  In a 990/10A, the mapper was on a 64-pin ASIC.  (The CPU only had 40 pins!)  This CRU interface ought to easily interface to an LS610 (99610) or 612.

Two: it describes the 16-bit Error Status register which was part of 990/10 and /12.  At  CRU 1FC0-1FDE.
 

3. The status register diagram is photocopied from a 990 manual, with penciled in:

ST10, overflow interrupt enable (99105 has this)

ST11, internal XOP enable (branches to writable control store, defined on 990/12.  On 9995 and 99105 it means XOP in progress)
 

4. Macrocode is not mentioned at all (feature of the 99105). 
 

5: Several pins not on a 99105:

 

WAITGEN. Said to generate wait states regardless of READY.

 

With the Attached Processor Interface is the PINT pin, Pending Interrupt.  It tells an AP that the CPU has an interrupt and is going to discard the pre-fetched instruction, so the AP better not execute it.  (An AP could be a second 990/10, or the Ten-X COBOL accelerator recognizing an XOP.) (The 99105 APP pin is named XIPP here, as in the SBP9989.)  

 

(There are no pin numbers, but I count 44 signal names...)


***

 

There's a 3-page memo by Harvey Cragon on Attached Processors.  Cragon was architect of Texas Instruments'  supercomputer, the ASC, and worked on the TMS32010. 

 

Cragon became Professor of Computer Science at UT Austin and wrote a good entry-level book on computer architecture.  
 

One thing I like about Cragon's book. Other texts meekly invent some boring RISC instruction set to illustrate Harvard and von Neumann architecture.
 

(background: separate memory for code and data is Harvard, von Neumann means code and data together in same memory. 9900 was von Neumann.) 

Cragon's approach is bad-ass:   If we're going to understand von Neumann, we're going to learn the actual von Neumann computer. Made-up examples don't teach how the real world forces you to  choose trade-offs.  

 

This machine didn't have a conditional branch (like JEQ, JNE.)  Instead, you modified the next branch instruction by adding a result to its jump target. 
 

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TMS9940

 

Copies of the thin data book.  
 

This was a cursed CPU: it had so many bugs, Texas Instruments withdrew it from production.  But it gave its name to the Home Computer. 
 

The 9985 was also doomed (or was it the same thing?) 

 

It would have an 8-bit data bus and fit into a 40-pin package.  Like the 9981, it addressed just 16K (up to 3FFF.) There is on-chip RAM at 8300-83FF.  With just 16K address space, you would need some way to get to more memory outside. (GROM anyone?)
 

It was designed to be the inexpensive baby member of the 9900 family. (I thought the 9981 filled this niche--it's in peripherals like the disk controller of the big desktop 990/1.)
 

There's a related report here by Adam Osborne (yes, that Osborne!)  It critiques the 9940/85 in scathing terms. At the end, Osborne's suggested pin out shows bidirectional I/O ports, much like the TMS7000.  
 

 Karl Guttag's second success at TI was a re-design of the doomed 9985, which  became the wonderful 9995.

 

 

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TM990/1481


1481 was positioned as the "High Performance CPU." It cost $5500 and occupied two slots of a TM990 chassis. 

 

Its two big manuals are not in DeGolyer (90% sure.) Instead, I read them from Colin's website.  They document every detail internal to this CPU, exactly parallel to the details of the 990/12 in the  MDS-990 book. 

We thought 1481 might be a slimmed down FX990, the 990/12 on two cards, because both used the 74S481 bit-slice processor.  Nope.  
 

The microcoding documentation teaches every detail of the CPU's inner workings.  
 

1481 has the 99110 instruction set, and its micro-architecture is vastly different from the 990/12.
 

The /12 runs on a 4-phase clock, just like the 9900 and 99000. The 1481 does not.

 

The intriguing feature of the 1481 is a variable clock period from 66 to 666 nanoseconds.  It uses a 15 MHz crystal base.

 

Each 1481 micro instruction might take as little as 66 ns. If the operation needs more propagation or settle time, it is coded to wait up to 9 extra periods.

 

All other 9900s executes a micro-instruction over a 4-phase internal clock, making one machine cycle. For instance, every 9995 micro instruction occurs over 4 phases or one machine cycle of 333 ns. 
 

With the 1481's variable clock,  it's possible that some operations could be more efficient on the 1481 than even the Alpha.  Even though 1481 is an enormous  circuit board compared to the Alpha chip (41 sq mm?) 

 

To make things fair, suppose an Alpha clocked at 16 MHz in. The internal cycle is 1/16M or 63 ns. Four make one machine cycle or 250 ns.  Suppose an instruction taking 6 cycles, or 6 micro-instructions, for 1500 ns. 
 

Clearly, a 1481 would might need 4 micro instructions to have the same outcome. But sometimes it might be fewer! Maybe one phase is sometimes idle time.  
 

A 9995 bit shift (SRC, SLA, etc) takes an extra cycle per bit position, or 333ns. A 1481 could potentially shift one more position in 66 or 132 ns, then repeat. You get the idea. 
 

The beauty of writing your own microcode is that you get to eliminate redundancy inside instruction sequences. Imagine fused multiply-add, or multiply-divide with 32-bit intermediate.  As two instructions, you write and read the intermediate result.  Whereas two instructions fused into one might avoid four cycles of intermediate write/read. 

 

The TMS7000 offered user mask ROM, with user-supplied microcode that might take  40-60% of the time of using assembly code.  Colin used microcode to meet timing in a custom chip. 

Assembly language seems efficient... until you realize there's another layer underneath, the microcode. 
 

 

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23 hours ago, FarmerPotato said:

(CROM is where the microcode exists in the CPU. Make your Conan the Barbarian jokes!)

conanthebarbarian-kingofthievesonhisthrone.thumb.png.c62d0aa936228ed1ba65753d7b78fabe.png

Conan, King of Thieves, is pleased with your raid upon the archives.  He says, Crom smiles at you from high upon his mountain, where he welcomes your answer to the Riddle of Silicon, which shall earn you welcome into Valhalla and the many treasures within.

3 hours ago, FarmerPotato said:

This machine didn't have a conditional branch (like JEQ, JNE.)  Instead, you modified the next branch instruction by adding a result to its jump target.

This is just plain sorcery: induced self-modifying code.

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