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How to lock the F18a and halt F18a CPU


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I read the documentation and looked at the register excel file, but questions remains (and I'm assuming I'm doing something wrong in Stevie)


  1. What is the proper way to halt the emulated TMS9900 CPU in the F18a?
    Is it sufficient to use the IDLE instruction as last line in assembly program
    or do I need to halt the CPU in the F18a GPU by writing 0 to extended register VR56 (>38) ?
  2. What is the proper way to lock the F18a GPU after it has been unlocked?
    Is it sufficient to write >00 to extended register VR57 (>39)?  
Edited by retroclouds
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Just to be clear... When you say "lock the f18a GPU" do you mean restoring the VDP to 9918A mode, or just locking the 9900 GPU functionality?


For restoring to 9918A:

I restore palette 0 - https://github.com/jedimatt42/fcmd/blob/d52d0a838d354c9b38a3d7ebea0e37eecf112c3d/b7_palette.c#L19


And use a reset registers command register, VR0x32 = 0x80,


And then I generally setup an EA5 like environment...VR0x02 = 0x00...  etc...

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Seems like the only way to halt the GPU in isolation, is to as you said, set VR0x36 and VR0x37 to the location of an IDLE instruction. If you have any of the GPU triggers set, such has hsync or vsync you'd want to disable those also..


resetting the registers with VR0x32 = 0x80 also disables the triggers (since they are set in registers) and presumably the GPU address. 

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  • 3 weeks later...

Sorry for being late to the conversation.


To "relock" the F18A, i.e. prevent writing to VRs over 7 and disabled the enhanced modes for colors and patterns, just write any value to VR57, or write >80 to VR50.


VR50 (>32) bit >80 will do a "register" reset to the power-on state of the VDP, which is all zero "0" in every register with the exception of:


VR1 = >40 (no blanking, the 4K/16K bit is ignored in the F18A)

VR3 = >10 (color table at >0400)

VR4 = >01 (pattern table at >0800)

VR5 = >0A (sprite table at >0500)

VR6 = >02 (sprite pattern table at >1000)

VR7 = >1F (fg=black, bg=white)

VR30 = sprite_max (set from external jumper setting)

VR48 = 1 (increment set to 1)

VR51 = 32 (stop sprite to max)

VR54 = >40 (GPU PC MSB)

VR55 = >00 (GPU PC LBS)

VR58 = 6 (GROMCLK divider)


The real 9918A will set all VRs to 0, which basically makes the screen black, blank, and off, 4K VRAM selected, and no interrupts.  I did not find that very useful, especially for troubleshooting since you could not tell if the F18A was working or if the system was having a problem, so I set a few sensible defaults to allow the screen to display something.


Note that nothing restores the F18A palette registers to the power-on defaults, other than a power on.


As for the GPU, the VR50 >80 reset will *not* stop the GPU, and if the GPU code is modifying VDP registers, then it can overwrite the reset values.  However, since the reset does clear VR50, the horizontal and vertical interrupt enable bits will be cleared, and thus the GPU will not be triggered on those events.


The reset also changes VR54 and VR55, but they are *not* loaded to the GPU PC (program counter).  The only events that change the GPU PC are:

* normal GPU instruction execution.

* the external hardware reset.

* writing to VR55 (GPU PC LSB).

* writing >00 to VR56 (load GPU PC from VR54 and VR55, then idle).


So, for the sake of "resetting" the F18A to a state where it will behave like the 9918A (or a fully power-on state), this would be the sequence:


1. VR56 = >00 (reset and load the GPU PC.  Don't care what VR54 and VR55 are, the GPU will be idle).

2. Restore palette registers 0..15 if necessary.

3. VR50 = >80 (reset VDP, which will also relock the F18A).

4. Set VR0..7 as necessary.


If you never use the GPU or mess with the palette, then you can probably get away with just writing >80 to VR50 and then BL @>0000.


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I probably changed it when I added the graphical initialization of VRAM.  Corresponds to this:




Note that the VRAM is *not* initialized with the VR50 reset or even the external reset pin.  The only time VRAM is initialized is power-on when the FPGA loads its bit stream.


Power-on initialization under emulation does not really have to match the F18A unless you want it to. You could write whatever you want to VRAM.  I made this change mainly to help with troubleshooting hardware problems.

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There are 64 palette registers and each is 12-bit, so 4096 possible colors.  Each color component is 4-bits, so 16 levels of each red, green, and blue.  I don't know if there are any programs that exercise the palette registers.  Check the F18A demos Rasmus wrote.  Also, I'm pretty sure Zaxxon is using the colors from the original arcade, so that would be an example.


Edit: there is also the image viewer Tursi wrote:


Edited by matthew180
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