TailChao Posted February 19, 2022 Share Posted February 19, 2022 The paragraphs below are snipped from an exchange between @RevEng and myself regarding HALT's behavior from the perspective of a cartridge. While nearly all of their contents are available on the board in some form - this is the tidied up and easier to read edition. I feel this should be public knowledge for the sake of clarity, hardware preservation, and the development of more elaborate game software. ... To be clear before advancing - many of the design choices made when we were doing Rikki & Vikki's hardware were defensive based upon common 6502 platform quirks. So if you're reading through the mapper Verilog and something seems over-engineered, it's probably there because I didn't want to live on the edge when selling a product for actual cash money. Uh oh, it's time for a diagram... [Not fond of pbrush.exe? Here's a scope trace originally from this post...] I think I've posted the "second falling edge of PHI2" quip until I was blue in the face (or I guess red in the fingers) and I've yet to encounter a case where it doesn't hold up. Back in 2015 when the mapper was being designed, I wasn't sure whether Maria would actually adjust her bus capture timing depending upon Sally's accesses after HALT lowered - so I made a kludge around it. SOUPER (and by extension the unfinished PMC1) separate and gate R/W into /OE and /WR using PHI2, then decode all chipselects purely based upon address - this removes a lot of other unnecessary headache so I recommend doing the same. Once we detect Maria has the bus /OE is held low until HALT rises again (as Maria only reads and R/W stays high during her DMA). Okay, good so far... Now the kludge - we know Maria is going to take the bus somewhere during the second PHI2 cycle, and her first read is going to be a Display List entry. So I just dumped the Display Lists (and DLLs, to be safe) into a region of memory which has the same mapping when either Sally or Maria has the bus. As long as there's no weird glitches during the handoff, it'll work (and it did). That's basically it - don't enable your Maria paging until two falling edges of PHI2 after HALT drops, and separate R/W into /OE and /WR. Now there are sharp edges in terms of signal integrity and the need to accommodate this in your board layout - in particular HALT, PHI2, and R/W. My handmade prototypes were actually unstable on certain machines (mostly PAL boards), and Tiido took a lot of precautions to make sure these three would run straight to the mapper PLD with thick traces and zero meandering - this is one of several reasons I think Curt had so many issues with the XM. There does seem to be a fondness for peeing all over the lower address space here, and I'm not really okay with it. For one because of how Atari / GCC chose to enable the cartridge slot, and also since you have no idea what weird stuff might be shoved between the console and your cartridge in the timespan of now until the universe collapses - but that's up to you. I do need to give two disclaimers - while the Maria design materials Curt found are extremely helpful, we're not going to have a full (proper) understanding of the production die until someone puts up the dosh to decap the chip. Also, my logic analyzer and 7800 never had the chance to meet before I moved on to other things - so while everything above is quite sturdy (any issues reported with Rikki & Vikki were always the console aging or just being broken), it's still an elaborate guess. Most of my own work was based upon this trace by nichtsnutz from 2014, which really gave away the keys to the bus so to speak. 8 2 Quote Link to comment Share on other sites More sharing options...
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