SIO protocol

[atariksi]

I haven't read anything about POKEY requiring more than one cycle to pass data through shift register. It should handle the full throttle 1.79Mhz through its shift register. It should be able to save the bit and shift the contents. The delays would be caused by processing the bytes that come in.

 

May be you haven't read it can't shift in a single cycle, but I'm sure you never read it can, didn't you?

 

For sure the whole serial (both in and out) logic can't work at "full throttle". For starters because there are synchronous edge detectors in the clock generation. This means that the serial clock (either internal or external) must be, at the very least, one cycle high and one cycle low. Otherwise, if it is as fast as the main clock, then no edge would be seen, and no pulses would be generated. So a "full throttle" clock would be the same as no clock at all.

 

In second place, the Pokey shift registers can't shift not even in two cycles, let alone in a single cycle. Of course that it is possible to make a "single cycle" shift register, but it would require more transistors.

...

In regards to POKEY, don't agree with that-- full throttle clock is same as no clock at all. I think I should be able to prove my claim by transmitting some serial bytes at 1.79Mhz through a fast LPT port.

 

All circuits are assumed to work according to spec unless you can prove otherwise so according to spec. POKEY should be able to deal with a bit coming in at 1.79Mhz and shift it as it shifts at other rates. Even if it's a cycle or two behind in shifting and receiving, at least it can deal with all the bits coming in.

 

>

Those crystals are for color carrier generating and because of that are far more accurate than the average crystal you will find in computers. Usually you will find a 4x color carrier frequency crystal (4x for easy 90° phase shifting of the wave).

 

>Nice theory. Now go and hook a scope to any Atari computer and see how accurate they are. Even if they were accurate when they came from factory, crystals have a considerable aging effect.

 

>Besides, and once again, the nominal freq. value is not exactly the same on all models. So even if they would be the most accurate crystals in the world, you still can't talk about that precision across all models.

 

All the WSYNC-based software or cycle-exact software relies on timing being consistent throughout all models and all of my old Ataris still have the same timing in tact. And this cycle-exact programming is documented.

[MEtalGuy66]

How much deviation does a crystal generally have due to aging?

 

Does it make them less accurate, or actually shift their frequency one way or the other?

[candle]

xl series without freddie chip have clocks multiplied by 4, xe and all that have freddie - by 8, and this is important, but not for this case

 

Rybags: proceed and interrupt are input signals, and pia is able to raise interrupt - good for slow devices, but not for fast transfers, but we can use motor_on and command

reason was to signal pc that atari software didn't recived byte and pc have to wait before sending next byte

from atari sfotware point of view reciving sector could look like that:

 

1 read data from serin

2 toggle motor on (make it 1, then 0 again, no wait, just pulse)

3 store to memory location

4 increase pointer

5 decrese byte count (loop)

6 if byte count is not 0 then jump to 1

 

practical implementation:

	ldy	#255
loop
cycles
0	lda	SERIN
4	ldx	#%00111000
6	stx	PACTL
8	ldx	#%00110000
12	stx	PACTL
16	sta	(Buffer),y
22	dey
24	bne	loop
27 cycles per revolution 64kbytes/s fully synchronized with pc

you may say byte order is reversed, but this is only true if pc side won't send it reversed too

it might be also not exact cycle count, since i really don't know 6502 verry well

[Bryan]

How much deviation does a crystal generally have due to aging?

 

Does it make them less accurate, or actually shift their frequency one way or the other?

 

I believe what we're talking about is a little bit of frequency drift from the ideal. Crystals are rated by their resonance frequency tolerance (in ppm) when new, and how far they may drift with age.

 

The other type of error is cycle-to-cycle inconsistency (called jitter) and is predominantly a function of the oscillator circuit design.

Edited February 9, 2009 by Bryan

[ijor]

In regards to POKEY, don't agree with that-- full throttle clock is same as no clock at all...

 

I'll try to post a picture later and you would understand what I meant.

 

All circuits are assumed to work according to spec unless you can prove otherwise so according to spec. POKEY should be able to deal with a bit coming in at 1.79Mhz and shift it as it shifts at other rates. Even if it's a cycle or two behind in shifting and receiving, at least it can deal with all the bits coming in.

 

Nowhere in the specs it is mentioned the max rate of the serial clock. And I think you are completely misunderstanding the issue. The issue is not the absolute frequency, the issue is the relation between Pokey main clock and the serial one. If you would overclock Pokey, and assuming it would work reliably, then you could increase the serial clock as well.

 

I think I should be able to prove my claim by transmitting some serial bytes at 1.79Mhz through a fast LPT port.

 

Please do it.

 

All the WSYNC-based software or cycle-exact software relies on timing being consistent throughout all models and all of my old Ataris still have the same timing in tact. And this cycle-exact programming is documented.

 

We are talking about oranges and you are replying about apples. We are talking about the accuracy of the crystal/oscillator in relation to its nominal value. This has no relation whatsoever with cycle-accurate software. You could use a crsytal that is out by 10% of the nominal frequency, and/or with a lot of jitter, and cycle accurate software would still work.

[ijor]

How much deviation does a crystal generally have due to aging? Does it make them less accurate, or actually shift their frequency one way or the other?

 

I'm not sure, but I believe both. Possibly one is affected more than the other.

 

I read a very interesting app note some time ago about this. It was at one of the crystal/oscillators manufacturers. It explained things such as manufacturing accuracy, tolerance to temperature variations, and aging. I'll see if I could find it again.

 

xl series without freddie chip have clocks multiplied by 4, xe and all that have freddie - by 8, and this is important, but not for this case

 

I'm not talking about this (wasn't it obvious?). I am talking about different nominal values that would affect the PHI2 clock, after division.

 

Go to Best Electronic web site, you would see how many different (with similar frequencies) crystals they have. I understand that 800/400 use one value, 600XL use another, 800XL and later a third one. Conceivable, it depends even on the board revision.

 

The difference is, of course, tiny, it shouldn't matter in real life. I raised the issue in reply to Frohn, that was attempting a precision of don't know how many digits.

[Rybags]

atariski: the limitation per cycle is easily explained. Imagine the High/low transitions of computer clock and serial input clock:

 

Computer HLHLHL etc.

Input: HLHLHL etc.

 

Of course in the real world they probably won't be aligned. But Pokey does it's work/samples the input clock only at a specific part of the cycle. So, like ijor said, it will only be seeing that one part of the input clock's cycle. To work, it will need to run at half of Pokey's clock rate (assuming if Pokey can in fact receive at that rate).

 

candle: with the Int/Proceed thing, I meant for the program to actually read the PACTL/PBCTL registers, not actually have any IRQs being serviced via those input lines.

 

What's with the Motor Control thing? Will you be just using that to signal your to your device that a byte has been received?

[candle]

ijor: i don't want to be the rude one again, but i think this thread is not only about oranges, apples and other juisy fruits, but also about current sex affairs, art of zen, and bonsai trees

this started as sio protocol, because of me moved toward speed limits of sio transfers, but now?

 

to all: please don't write its impossible to do this or that, or that atari has capacitors on data lines

those who want to keep their atari as genuine as it could be should keep transmission at 19200 for disk drive, 600 for tape recoreder, and 300 for modem, anything more than this should result in curse in whole familly..

 

i'm trying to be sarcastic here, but i'm trying to make a point

life is too short for argues about the obvious, keep that in mind

 

one more thing:

ijor: i was asking you to show me part of schematics when clock is being synchronized by phi2, you've replied thats is internal to pokey - okay, i never thought otherwise, but i was asking about that internal schematics of pokey...

schematics i've seen don't have such mechanism shown

i'm using http://asap.sourceforge.net/pokeydoc.zip as a reference schematics, and i can't find anywhere that input clock is synchronized with phi2

[candle]

Rybags: its an idea - but 64kbytes per second is not that hard to reach

[ijor]

one more thing:

ijor: i was asking you to show me part of schematics when clock is being synchronized by phi2, you've replied thats is internal to pokey - okay, i never thought otherwise, but i was asking about that internal schematics of pokey...

schematics i've seen don't have such mechanism shown

 

Oh, I see, sorry. See attached picture with three outlined rectangles in red:

 

 

Bottom left: Bi-clock being synchronized with PHI2.

Bottom right: Edge detector and pulse generator. Yet again, another PHI2 synchronization, of course.

Upper right: Shift register control. This is the logic that (if I'm not mistaken) would require a minimum of 3 clocks per bit.

 

to all: please don't write its impossible to do this or that, or that atari has capacitors on data lines...

 

You might be right. But I don't see anything wrong when HIAS warned you about them. You further replied they are not common, which I doubt it is correct.

 

I also believe those caps are there for a reason. But I won't elaborate unless you insist

[ijor]

i'm using http://asap.sourceforge.net/pokeydoc.zip as a reference schematics, and i can't find anywhere that input clock is synchronized with phi2

 

I just realized that you might be looking at the re-created logic diagrams, and not at the original schematics.

 

In general, the work that they (Perry and Piotr) did in the logic-diagrams, was more emulator oriented than anything else. These kind of details we are talking about, are mostly not reflected in the diagrams.

[+poobah]

and let us not forget our good ol' friend nyquist.....

[Fröhn]

Nice theory. Now go and hook a scope to any Atari computer and see how accurate they are. Even if they were accurate when they came from factory, crystals have a considerable aging effect.

Atleast the PAL C64 crystals of 17.734475 MHz seem to be quite accurate when comparing different machines. Less accurate are the 16.000 MHz crystals of the 1541 drives. Actually only on the drives I was able to measure a difference (about 3/10000 between different drives).

 

Besides, and once again, the nominal freq. value is not exactly the same on all models. So even if they would be the most accurate crystals in the world, you still can't talk about that precision across all models. And I'm not talking about NTSC vs PAL.

The color carrier is directly generated from that clock, if it was all too different you would have color tone shifting within a rasterline.

[candle]

i'm looking on page you've posted here and still don't have anything synchronized, maybe i missing something, but parts in red may be for delay and edge detection rather than phi2 syncing

material contained in pokey.pdf is pretty useless, since its readibility is - to say the least - limited

i wonder if there is paper version of this which could be scanned in proper resolution not as bitmap (only black and white), but at least in grayscale

[candle]

phoobah: please... don't... just don't

[ijor]

i'm looking on page you've posted here and still don't have anything synchronized, maybe i missing something, but parts in red may be for delay and edge detection rather than phi2 syncing

 

I don't know how much you are familiar with "classic" NMOS ASIC schematics. If you are looking for synchronization done with edge-triggered Mater/Slave flip-flops, then you aren't going to find them. These aren't modern designs, clock synchronization is done with simple phase clock couplers between gates and "dynamic" cells.

 

Now, look at the three inverters to the right of the Bi-Clock pad. The second and the third one are "clocked" inverters, there is a clock coupler on each inverter input. Coupler means a mosfet switch transistor that can connect or disconnect both ends. Clock coupler means that this mosfet is controlled by one of the phases of the clock. The second inverter has a phase 2 (PHI2) clock coupler, the third one has a phase 1 (NOT PHI2) clock coupler. Together, both inverters behave functionally exactly like a "modern" flip-flop synchronizer.

 

There are similar clocked gates in the other two sections I outlined.

 

i wonder if there is paper version of this which could be scanned in proper resolution not as bitmap (only black and white), but at least in grayscale

 

Not currently, but hopefully we'll see them shortly.

[candle]

ijor: can you give me some source for information about nmos asic design? i was expecting such things like clocked inverters may exist, but would really like to get some perspective and broaden my knowledge

[ijor]

Nice theory. Now go and hook a scope to any Atari computer and see how accurate they are. Even if they were accurate when they came from factory, crystals have a considerable aging effect.

Atleast the PAL C64 crystals of 17.734475 MHz seem to be quite accurate when comparing different machines. Less accurate are the 16.000 MHz crystals of the 1541 drives. Actually only on the drives I was able to measure a difference (about 3/10000 between different drives).

 

1 - I didn't know that the C64 was an Atari computer. May be they have much better crystals, I don't know.

2 - If you can't measure difference across multiple Atari computers, then you are probably not using a scope good enough. See some captures posted here by Ken, and you'll see a sample of what I'm talking about.

3 - You are talking about 3/10,000 as it was tiny. But OTOH, when you corrected Hias claiming a "precision improvement", your correction was in the eighth digit! May be my math is too weak, but both scales seem to be a world apart!

 

The color carrier is directly generated from that clock, if it was all too different you would have color tone shifting within a rasterline.

 

Nobody said they are "all too different". They are just not that identical in the "precision improvement" scale you were talking about. You don't agree, then tell Best Electronics to stop selling "bad" (according to your logic) crystals.

[Fröhn]

1 - I didn't know that the C64 was an Atari computer. May be they have much better crystals, I don't know.

C64 and A8 are very similar when it comes to their clocks and video signal generating. Those crystals are normally used in other PAL/NTSC equipment and are more accurate than the average computer crystal.

 

2 - If you can't measure difference across multiple Atari computers, then you are probably not using a scope good enough. See some captures posted here by Ken, and you'll see a sample of what I'm talking about.

I wasn't using a scope at all. I measured the differences between different models via phase shift over time measurement C64 vs 1541. It showed that if you swapped 1541s, you get some noticable difference but if you swapped the C64s the phase shift would not change.

 

3 - You are talking about 3/10,000 as it was tiny. But OTOH, when you corrected Hias claiming a "precision improvement", your correction was in the eighth digit! May be my math is too weak, but both scales seem to be a world apart!

3/10000 on the 16.000 MHz clock of the 1541. I was not able to measure any difference between different 17.734475 MHz crystals of the C64.

[ijor]

ijor: can you give me some source for information about nmos asic design? i was expecting such things like clocked inverters may exist, but would really like to get some perspective and broaden my knowledge

 

I'm afraid I don't know about a good reference. I just learnt it the hard way, looking at this type of schematics and doing a bit of research. I'm not even sure that the terminology (such as "clocked gate") is 100% correct. A possible idea might be to download the TIA (the custom chip of the 2600) schematics, they are available to download here at AtariAge in full high rez. After some analysis you eventually come to understand the main ideas. What I can do is to briefly mention some concepts I learnt that I found very helpful:

 

These are tiny devices for modern standard, with a very limited transistor budget. They have something in the order of a few thousand transistors. Every transistor counts! Consider e.g., the serial register we are talking about here. If you save a couple of transistors per bit cell, that's 20 transistors you save in the whole shift register. You then saved something close to 1% of the whole IC, that is significant! Perform just a dozen of similar optimizations, and you saved 10%. This might make the difference between reaching your transistor budger or not.

 

These aren't fully static devices, they have a lot of dynamic cells. Same reason again, dynamic cells need less transistors. Fully static vs. dynamic is still a modern topic, so you should be able to find many on-line references.

 

If you are familiar with high-speed modern synchronous designs, then just forget everything you learnt. There is no ultra rigurous treatement of clocking. I understand that TIA (which is a few years earlier) uses almost every conceivable ripple/gated clock technique that would be considered "shock-horror" nowadays.

 

So how something like a couple of "clocked" inverters works: There is a mosfet switch at the input of each inverter. At each phase of the clock, one of those switches is "open". The inverters have then their input floating on high impedance, but they retain (latch) their previous value due to their capacitive charge (that's why they are dynamic cells).

 

This works, for synchronization and delay purposes, like an edge-triggered flip-flop. A signal coming to the pair of inverters, would take two clock phases (one full cycle) to reach the output of the second inverter.

[MEtalGuy66]

to all: please don't write its impossible to do this or that, or that atari has capacitors on data lines...

 

You might be right. But I don't see anything wrong when HIAS warned you about them. You further replied they are not common, which I doubt it is correct.

 

I also believe those caps are there for a reason. But I won't elaborate unless you insist

 

If we are talking about C301-C310 (the caps on the SIO port) , those caps are there on every NTSC 130XE and 65XE that Ive seen. And I've seen the inside of quite a few of these machines since the 80s.

 

They are put there to comply with rediculous FCC regulations that were in place when the machines were made.

 

None of the PAL machines I've seen have these caps populated.

 

And I have removed them from quite a few NTSC machines, because they cause problems with disk access (specifically high-speed access on 1050 and Indus drives, and they even cause quite consistant errors with normal speed on the XF551).

Edited February 10, 2009 by MEtalGuy66

[supercat]

Nobody said they are "all too different". They are just not that identical in the "precision improvement" scale you were talking about. You don't agree, then tell Best Electronics to stop selling "bad" (according to your logic) crystals.

 

IMHO, it is useful and interesting to know the precise definition of colorburst being 1000/1001 times 30 frames/sec * 525 lines/frame * 227.5 cycles/line. That doesn't mean someone who doesn't specify it to the ninth place is "wrong", but merely that it's useful knowing where numbers come from. I still think that 1000/1001 multiplier is 'odd'; I understand that it's useful to have a number of clocks per line pair that's a multiple of small numbers (455=5*7*13) but I'm not sure why they chose 455 and then threw in the 1000/1001 kludge, rather than simply picking a different multiple (e.g. 495=5*9*11, or 429=3*11*13, or 441=3*3*7*7)?

[supercat]

If you are familiar with high-speed modern synchronous designs, then just forget everything you learnt. There is no ultra rigurous treatement of clocking. I understand that TIA (which is a few years earlier) uses almost every conceivable ripple/gated clock technique that would be considered "shock-horror" nowadays.

 

Actually, I'd say the reverse is true, in a sense. Many devices today use fully static designs driven by a clock which has minimum high/low times and a maximum rate, but no other requirements. Some devices use an internal clock multiplier which will only operate within a certain range of speeds, but the device logic itself doesn't care whether it's clocked fifty times per second or fifty million times per second. If the clock stops for a second, or even a year, the device will remain in the state it had just after the last clock pulse, and will resume functioning as soon as clock pulses start arriving again. At any given moment, all bits are securely "held" by part of the circuit. The operation of such a device might be likened to bucket brigade in which nobody lets go of a bucket until the next person has grabbed it.

 

Dynamic logic, by contrast, has far more rigorous timing requirements. If those requirements aren't met, things can malfunction very badly. A dynamic design might be likened to a line of people who are juggling objects among themselves. Each object that is passed will be released by the old holder before it is caught by the new one. If the new one isn't in proper position to catch the object, it will fall on the floor. Of course, actual people who are passing objects can adjust their timing if needed, but imagine a line of robots who were all wired to operate in tandem from the same control signals. If the timing on those signals isn't right, things will all come crashing down.

 

That having been said, there are straightforward ways of implementing dynamic logic and tricky ways, and nearly all of the TIA's dynamic logic fits the straightforward pattern: two-phase non-overlapped clocking. Most of the circuit modules in the TIA receive two clock signals which run in the sequence (low low) (high low) (low low) (low high). When a clock is high, the chips connected to that clock will drive their outputs according to their inputs; when the clock is low, the output will 'float'. An output which is floating will hold its state for a few microseconds; the output must be re-driven (meaning the inputs must have the correct data to do so) before that time is up. Two-phase non-overlapping clocks are pretty straightforward provided two requirements are met:

 

-1- The two clock phases must never be high simultaneously; their separation must be sufficient to allow all the devices controlled by one clock to switch off completely before any of the devices controlled by the other clock switch on.

 

-2- Neither clock phase may be allowed to go for too long without being active.

 

While the TIA contains two three-bit ripple counters, a divide-by-three for the CPU clock, and some two-phase clock generator circuits and miscellaneous latches, most of the chip is controlled via two-phase non-overlapping clocks.

[ijor]

I wasn't using a scope at all. I measured the differences between different models via phase shift over time measurement C64 vs 1541. It showed that if you swapped 1541s, you get some noticable difference but if you swapped the C64s the phase shift would not change.

...

3/10000 on the 16.000 MHz clock of the 1541. I was not able to measure any difference between different 17.734475 MHz crystals of the C64.

 

So what are you saying?

 

Are you saying that those crystals are so perfect (even after a couple of decades), that two C64's could be permanently "in sync" ?

 

Or, for that matter, are you saying that the precision of those crystals is better than 1 ppm, even after all those years?

[ijor]

Actually, I'd say the reverse is true, in a sense. Many devices today use fully static designs driven by a clock which has minimum high/low times and a maximum rate, but no other requirements...

Dynamic logic, by contrast, has far more rigorous timing requirements. If those requirements aren't met, things can malfunction very badly.

 

I wasn't talking about that "sense". I wasn't talking about the requirements or specifications of the clock signal. I was talking about a rigurous synchronous design, this has no relation whatsoever with fully static vs. dynamic. I mentioned both issues, but they are separate, not one directly related to the other.

 

Rigurours synchronous design means such things as no ripple techniques, no divided or gated clocks, no async latches or delays, etc. These are issues all valid disregarding fully static or dynamic cells.

 

I can't argue with you about TIA, or the 2600. But the A8 chipset, and the whole computer for that matter, violates most of these rules. And of course that I'm not complaining or blaming anybody about that. It was common practice at the time. Furthermore, it wasn't affordable to do that otherwise.

Edited February 10, 2009 by ijor