"Bad Apple" on cartridge

[+OLD CS1]

15 minutes ago, brain said:

Truly, it did.  It was like a jet engine's worth of "LAME" coming from across the room.

 

It was all I could do to not leverage it in some sick TI-platform burn from the Commodore table.

 

TI was representing.  Jealousy does not become you.

[brain]

4 minutes ago, OLD CS1 said:

 

TI was representing.  Jealousy does not become you.

?

 

[+OLD CS1]

Which brings me to another point.  Is it just me, or did we have a lacking of Commodore, Atari, and Apple presence?  The only Apple I remember seeing was the Laser 128 in the GUI history exhibit (which would be really neat to explain that it was an Apple clone.)  There were Ataris and Commodore 64s, primarily displaying telecommunications.  There was a really impressive mainframe exhibit.

[brain]

Every show instance brings different systems to the front. Except for the staples (you're going to see a bunch of CBMs at VCF-MW, since that show grew up around the ECCC CBM show, which came about due to the demise of the SWRAP CBM show in Chicago.  DEC is always well represented at VCF-E, since they have multiple models on site and a bunch of DEC-heads around that area), I've seen shows with No TIs followed by a year where they are everywhere.  Same for Atari and Apple.  Thus, I didn't note it too much.

 

Take the win, though. Your TI display was in great form. The GUI display just to the side of yours was very well presented and multi-platform, which is always a bonus.  The telephone exhibit was also nice, though I didn't spend much time there.

 

Jim

 

 

[+OLD CS1]

While proud of my displays, I am honestly not trying to take a victory lap.  I would love to see some Ataris and Apples, since both were present in my elementary and junior high schools (we had an Atari lab in junior high with a bunch of 1200XLs for word processing.)  These are ones that I could not support, since they were never part of my home life.  I could, however, put together a good Commodore display with demos, games, maybe my 128D running GEOS 128 or a 128 running CP/M (though, again, not many people care about another home computer running a command prompt.)

 

Yeah, I did not catch his name, but the GUI exhibit is really good.  I like that he does not limit the exhibit to Windows, he shows GEOS, another GUI with which I am unfamiliar, Microsoft Bob, and a couple of Windows versions including 1.0.

 

The phone systems are really cool.  I enjoyed helping a couple of kids learn how to dial the rotary phone.  One thing I notice is the youngin's are genuinely interested in this older technology.  I think it is great to help fill in some of the holes on what they know about the technology they use today.

 

I have backups of my System/34 library from high school.  I have a digital copy of the disks, but I think it would be interesting to load them up on the System/36 display.  Not sure they have a floppy drive with it, though.

[wierd_w]

...

 

I have *GOT* to get around to doing that full MIDI arbitration on the Tipi over telnet/direct socket.

 

It's such low hanging fruit.

 

The only thing I forsee as a hiccup would be distortion on mixing. There is 0 mixing hardware in the TI. How does it handle chip tune generation in conjunction with speech synthesis? Injecting monoaural audio in the speaker line used by the speech would need to be mixable with the sound chip.

(I am imagining using FluidSynth midi over UDP, coupled with speech synth lyrics. Would cut the data needed by the video processor significantly.)

[+mizapf]

9 hours ago, OLD CS1 said:

Ugh.  Boomers.

And increasingly proud of it, the more I hear that term. ?

 

I'm completely ignorant about the far east pop scene, manga and all. Luckily there is Wikipedia.

[TheMole]

Oh, I think the vast majority of us (exceptions notwithstanding) are mostly aware of it because of the plethora of retro computer ports. It has become a sort of coolness benchmark for these platforms...

Edited July 22, 2022 by TheMole

[+acadiel]

On 7/20/2022 at 11:25 PM, Tursi said:

Well, Eric's work notwithstanding, I could probably repurpose a DL cart board. I dunno what to do with them anyway, and I've offered in the past. People tend to ignore what I say.

 

Unfortunately, I don't have anything unpacked at the moment. 

 

As for it the player needing to be changed for the hardware - nope. 32MB of the cartridge works just like any other 32MB cart (assuming you always write the same data for the bank switch, anyway). It's only when you need to differentiate more than that that it becomes an issue.

 

 

Ah, so the limit then has been the 377 with the 8 latches (2MB).  A7 is the 2MB bank switch, A6 would be 4MB, A5 would be 8MB, A4 would be 16MB and A3 would be 32MB.  And A0-A2 I believe aren't on the cart port.

 

I think the reason @Ksarul made the 2MB board as the max is 1) that was the maximum parallel EPROM size that was 5V tolerant (and not all of them were capable of being 8 bit mode), and 2) the 377 with 8 lines is the largest "bank switch" chip without involving extra logic.

 

Edit: Did some reasearch, and the largest parallel EPROM that I can find is this one:  https://arcarc.xmission.com/Tech/Datasheets/27C320.pdf

 

4MB when configured to 8 bits.  Double the size of the one in the 2MB cart board and capable of addressing in 8 bits.  But in a SMT configuration (TSOP/SO).

 

The challenge would be getting a PLD to support the 9 lines needed for bank switching this sucker.  It can be done, though.

 

I have yet to find an 8MB or higher parallel 5V (E)EPROM.  Even the serial ones don't seem to go up very high.  Mouser's highest serial one is a 4MBit or 512K.  

 

[+acadiel]

10 hours ago, OLD CS1 said:

Which brings me to another point.  Is it just me, or did we have a lacking of Commodore, Atari, and Apple presence?  The only Apple I remember seeing was the Laser 128 in the GUI history exhibit (which would be really neat to explain that it was an Apple clone.)  There were Ataris and Commodore 64s, primarily displaying telecommunications.  There was a really impressive mainframe exhibit.

It's all about what people bring.  I did see several Commodores there, but the person that normally does the large Commodore exhibit either wasn't there this year or didn't bring much of their collection.

 

And yeah, they had a digital T1 line concentrator running through a different few concentrators and had analog BBS/telephone lines running to several exhibits.  

 

[brain]

Don't constrain by mandating 5V memory.  I found a creative way to address this with low parts count.  I use a big 3v3 flash with a small Xilinx CPLD and route all the address/data lines through the CPLD.  It's CPLD-wasteful per se, but makes the design super easy (2 ICs, 5 caps) for up to 8MB.  16MB would be 3 ICs.  While small CPLDs are in short supply right now, I bought 1000 of them many moons ago so I have ample stock.

 

Happy to lay one out, and I think it can be compatible with the 2MB PCB.

 

Let me know.

[+Ksarul]

41 minutes ago, brain said:

Don't constrain by mandating 5V memory.  I found a creative way to address this with low parts count.  I use a big 3v3 flash with a small Xilinx CPLD and route all the address/data lines through the CPLD.  It's CPLD-wasteful per se, but makes the design super easy (2 ICs, 5 caps) for up to 8MB.  16MB would be 3 ICs.  While small CPLDs are in short supply right now, I bought 1000 of them many moons ago so I have ample stock.

 

Happy to lay one out, and I think it can be compatible with the 2MB PCB.

 

Let me know.

Such a thing might come in very useful, especially if anyone wants to build cartridge images with a whole bunch of the compiled BASIC/Extended BASIC games in it. You could put nearly 500 of the 32K compiled titles on a single 16M cartridge. You will lose a little space for the header/loader, but it is very doable.

 

What do you plan to do to downshift the supply voltage to 3.3V?

[+acadiel]

7 hours ago, brain said:

Don't constrain by mandating 5V memory.  I found a creative way to address this with low parts count.  I use a big 3v3 flash with a small Xilinx CPLD and route all the address/data lines through the CPLD.  It's CPLD-wasteful per se, but makes the design super easy (2 ICs, 5 caps) for up to 8MB.  16MB would be 3 ICs.  While small CPLDs are in short supply right now, I bought 1000 of them many moons ago so I have ample stock.

 

Happy to lay one out, and I think it can be compatible with the 2MB PCB.

 

Let me know.

That would be an awesome layout - what gets a lot of us is the SMT part of the newer components.  Can it be extended to 32MB, which is the max cart size?  Would there just be a header to hook up to an ISP header on a programmer to program the chip then?  Be glad to help and/or test.  I really need to finish my Corcomp project - that thing is really tiresome to look at after long periods of time.

 

 

[brain]

On 7/22/2022 at 11:46 AM, Ksarul said:

Such a thing might come in very useful, especially if anyone wants to build cartridge images with a whole bunch of the compiled BASIC/Extended BASIC games in it. You could put nearly 500 of the 32K compiled titles on a single 16M cartridge. You will lose a little space for the header/loader, but it is very doable.

 

What do you plan to do to downshift the supply voltage to 3.3V?

Oops, sorry. 3 ICs Need a small linear VR there.

 

Jim

[Tursi]

On 7/21/2022 at 9:35 PM, OLD CS1 said:

Watching the demo in Classic99 made me wish the debugger could show bank switches.  ::demanding user intensifies::

I went back in time and implemented it for you.  It's the second half of the "bank" line, right above "DSR". First half is the bank mask.

[Tursi]

On 7/21/2022 at 9:32 PM, brain said:

But, it has to be doable and without a ton of work effort. THe TI is sometimes challenged in specs, but this cannot possibly be the showstopper.

It's doable and doesn't take a ton of work effort. I released a 128MB ROM, after all.

 

Latch the extra address bits from the address bus on a write (ignoring the least significant, since that can't be controlled), and you're done. It'll work with all existing code.

 

[brain]

22 hours ago, acadiel said:

That would be an awesome layout - what gets a lot of us is the SMT part of the newer components.  Can it be extended to 32MB, which is the max cart size?  Would there just be a header to hook up to an ISP header on a programmer to program the chip then?  Be glad to help and/or test.  I really need to finish my Corcomp project - that thing is really tiresome to look at after long periods of time.

 

 

It's been a few years since I looked at the cart port of the TI, but from the above discussion, it appears the max native cart ROM size is 8kB.  8 latches is then 256 8kB pages or 2MB.  Extending the latch to 16 bits would move far beyond 32MB (32 would only need 4 of the 8 additional bits.  But, I seem to recall there was a preferred TMS99XX way to send config information in a bitstream on bit 15 or something.  That's also easy to implement and would be cleaner, as no addressing would be needed into the ROM space.

 

Given the cart size and lack of stuff on it, a 2x3 or 2x6 JTAG header is easy to place.  But, since it's all SMT, if there was enough demand for the unit, I'd just run 100 units and program them here, so buyers would only need to load the files on them.

 

The 32MB version would probably be best to use PSRAM, as it's cheaper and can get in larger packages without going to full DRAM.

[Tursi]

On 7/22/2022 at 12:09 AM, wierd_w said:

The only thing I forsee as a hiccup would be distortion on mixing. There is 0 mixing hardware in the TI. How does it handle chip tune generation in conjunction with speech synthesis? Injecting monoaural audio in the speaker line used by the speech would need to be mixable with the sound chip.

By using the analog mixer built into the sound chip.  The cassette audio ends up routed through there too.

 

That said, it's completely hands off - there's no control of the mix at all.

[Tursi]

On 7/22/2022 at 8:57 AM, acadiel said:

The challenge would be getting a PLD to support the 9 lines needed for bank switching this sucker.  It can be done, though.

 

I have yet to find an 8MB or higher parallel 5V (E)EPROM.  Even the serial ones don't seem to go up very high.  Mouser's highest serial one is a 4MBit or 512K.  

That's why I used a CPLD. Had enough lines to manage both the bank switching and the voltage conversion. That said, even 5v tolerant CPLDs are getting hard to come by. ?

 

[Tursi]

20 minutes ago, brain said:

It's been a few years since I looked at the cart port of the TI, but from the above discussion, it appears the max native cart ROM size is 8kB.  8 latches is then 256 8kB pages or 2MB.  Extending the latch to 16 bits would move far beyond 32MB (32 would only need 4 of the 8 additional bits.  But, I seem to recall there was a preferred TMS99XX way to send config information in a bitstream on bit 15 or something.  That's also easy to implement and would be cleaner, as no addressing would be needed into the ROM space.

 

Given the cart size and lack of stuff on it, a 2x3 or 2x6 JTAG header is easy to place.  But, since it's all SMT, if there was enough demand for the unit, I'd just run 100 units and program them here, so buyers would only need to load the files on them.

 

The 32MB version would probably be best to use PSRAM, as it's cheaper and can get in larger packages without going to full DRAM.

32MB is the max without including the data bus, which is what I did for Dragon's Lair.

 

You get 8k stock. Since we're latching address lines, and since we can't use the least significant (which TI calls A15 because TI), we have A14 through A3 available. Latching gives us:

 

A14 - 1 bit - 16k

A13 - 2 bits - 32k

A12 - 3 bits - 64k

A11 - 4 bits - 128k

A10 - 5 bits - 256k

A9 - 6 bits - 512k

A8 - 7 bits - 1M

A7 - 8 bits - 2M  (current max cart available with single latch chip)

A6 - 9 bits - 4M  (demo cart built adding second latch chip)

A5 - 10 bits - 8M

A4 - 11 bits - 16M

A3 - 12 bits - 32M

 

Don't worry about the CRU (which is the bit 15 stuff you are thinking of), that's selected by a different select line. Just use the ROM select and the WRITE line to control the latch, and you're set.

 

(Edit: I just noticed you thought the CRU approach would be better - it's not available on all consoles. The later systems removed it from the cartridge port. Recommend sticking with the existing banking scheme.)

 

Edited July 23, 2022 by Tursi

[+OLD CS1]

59 minutes ago, Tursi said:

I went back in time and implemented it for you.  It's the second half of the "bank" line, right above "DSR". First half is the bank mask.

[brain]

/me shuffles off to look at how banks switching is done on TI.  Address lines, check. don't use A15 (a0 everywhere else) cause 16 bit to 8 bit translation, check.  No A2/1/0 on cart port, check.

 

How did you do 128MB, then?

 

Hmm, using address lines to select bank is std, but then how do I write data to the ROM space?

 

Jim

[Tursi]

4 hours ago, brain said:

/me shuffles off to look at how banks switching is done on TI.  Address lines, check. don't use A15 (a0 everywhere else) cause 16 bit to 8 bit translation, check.  No A2/1/0 on cart port, check.

 

How did you do 128MB, then?

 

Hmm, using address lines to select bank is std, but then how do I write data to the ROM space?

 

Jim

I added two lines from the data bus. But /only/ Dragon's Lair uses that.

 

You can not write data to the ROM space using this banking scheme. You'd have to make an exception or do something else.

 

TI started it, blame them.

 

[brain]

1 hour ago, Tursi said:

I added two lines from the data bus. But /only/ Dragon's Lair uses that.

 

You can not write data to the ROM space using this banking scheme. You'd have to make an exception or do something else.

 

TI started it, blame them.

 

I assume they did it to save ICs, as latching the address requires only no address decoding.  Sigh.  What a non future proof design tenet.

 

Ah, so a write latched the data lines, under the proviso that there's no other writes on the cart bus.  But, if that's the case, then why is not the Dragon Lair cart already used for this idea (Bad Apple)?  Seems like 128MB is already done.

 

Jim

 

[brain]

Can you do a 16 bit write to the cart part @ >6000 and if so, does the cart port see a $6000 write of 8 bits followed by a $6001 write of 8 bits?

 

Jim