MOVB bus semantics

[brain]

I know MOV is encouraged over MOVB given the 16 bit intrinsic size of the CPU, but I have a specific use case that demands byte write access and I am trying to determine if I can use MOVB to accomplish the goal.

 

The device is a FLASH ROM, which is 8 bit in data size.  As a ROM, all is well, it can be read just like any other ROM on the cart port.

 

But, to "talk" to it, one must write very specific values to very specific addresses in the ROM.  Any deviation will prevent talking to the FLASH device.

 

The specific values are unimportant, but many devices prepend all "commands" with an "unlock sequence", like sending aa to address x555, 55 to x2aa, 80 to x555, aa to x555, 55 to x2aa, 10 to x555, where X is don't care (makes it easier to hit the locations in a windowed ROM address map).

 

But, I need to validate that a MOVB would be seen as a single byte access at the cart port.  If 2 writes are done, the unlock sequence will fail and another solution would be required to issue commands to the FLASH IC.

 

I'm not very knowledgeable on the TI cart port bus semantics, so I thought I would ask.

 

Jim

 

 

Edited July 28, 2022 by brain

[+mizapf]

The TI system cannot write single bytes. You always have odd address - even address write operations. This is the reason why the CPU fetches a whole word before writing a byte, because it must get the unaddressed byte to write it back.

 

The Geneve with its TMS9995 can write single bytes, though.

[brain]

That is truly unfortunate.  I guess I'll have to create an indirect way to write to the FLASH ROM.

 

Jim

[+mizapf]

And if you check the A15 (LSB) line?

[Tursi]

7 hours ago, brain said:

That is truly unfortunate.  I guess I'll have to create an indirect way to write to the FLASH ROM.

Yeah, on my system for programming the flash I added a register I could write to that told the CPLD to pass only even bytes, only odd bytes, none or both (just two bits ).

 

The other approach, like mizapf hints at, is to ignore A15 and space everything by 2 instead of by 1. But you still have to deal with the fact that two writes would happen, which will break the flash sequence.

 

 

[apersson850]

This is why things like the VDP's write address, read address, write data and read data addresses are never adjacent. They are always spaced at least two bytes apart. Thus the second byte goes into the air, so to speak.

[+InsaneMultitasker]

On 7/28/2022 at 5:39 PM, mizapf said:

The Geneve with its TMS9995 can write single bytes, though.

This is one reason the Geneve can so 'easily' use and program chips like the 29c040 (and similar variants) without the need for special hardware. 

 

Some of the SNUG /4a cards make use of flash chips for DSRs and other purposes. The chips are programmed by loaders or on-card software.  I've never looked closely at the circuitry to know what magic is employed or what, if any, restrictions there are for compatibility. Might be worth reading related literature.