Ecernosoft Posted August 17, 2022 Share Posted August 17, 2022 Hello! Do any of you have the source for any stock (NO DSP!!!) 1 scanline kernals? I don't mind if they use extra RAM or bank switching, just they must comply to these two rulles: 1. No DSP or DCP or DCP+. 2. Must be one scanline kernal. (I don't mind if some things like missiles or the back-ground act like a 2 scanline kernal, just the players must both be one scanline.) Oh, and if it's ASYMETRICAL, that's even better. Thanks! Quote Link to comment Share on other sites More sharing options...
Ecernosoft Posted August 17, 2022 Author Share Posted August 17, 2022 Please, I'm not as smart 2600-wise than 7800. I can do almost anything in 7800 but Line kernals on 2600 are where I struggle. Quote Link to comment Share on other sites More sharing options...
Ecernosoft Posted August 17, 2022 Author Share Posted August 17, 2022 Also, apparently you can draw a multicolored sprite in 28 cycles. How can you do that? Quote Link to comment Share on other sites More sharing options...
+SpiceWare Posted August 17, 2022 Share Posted August 17, 2022 DoDraw can draw a multicolor player in 26 cycles. If you use a mask you can knock that down to 21 cycles, from Stay Frosty, Part 3: lda (FrostyImagePtr),y ; 5 5 and (FrostyMaskPtr),y ; 5 10 sta GRP0 ; 3 13 lda (FrostyColorPtr),y ; 5 18 sta COLUP0 ; 3 21 I posted a mask demo with source in this topic. It's a monochrome demo so you'd have to add the LDA/STA COLUP0 1 Quote Link to comment Share on other sites More sharing options...
The Brew that is True Posted August 17, 2022 Share Posted August 17, 2022 In my experimental WIP I'm using a single-scanline resolution kernel for the Player sprites (spliced with a 4LK for the PF and BL). Here's an excerpt: --------------------------------------------------------------- DK WORK 1/17 - 1LK TIA Updates - 1st of 4. Color Clocks: 27 x192/4 = 27 x48 = 1,296 ROM Bytes: 6 --------------------------------------------------------------- Update TIA Player Graphics registers. N.B. Assumes preloaded A register. 851c sta GRP1_ff (3)x3 @ dk.000*.000-008 *** a5d2 lda ORAM_GRP0 (3)x3 @ dk.000*.009-017 851b sta GRP0_ff (3)x3 @ dk.000*.018-026 *** --------------------------------------------------------------- DK WORK 2/17 - 4LK TIA Updates. Color Clocks: 63 x192/4 = 63 x48 = 3,024 ROM Bytes: 14 --------------------------------------------------------------- Update TIA PF Graphics and Ball Enable registers. TODO This is temporary test code. a5d3 lda ORAM_PF0_BL (3)x3 @ dk.000*.027-035 850d sta PF0_f0 (3)x3 @ dk.000*.036-044 *** 851f sta ENABL_02 (3)x3 @ dk.000*.045-053 *** a5d4 lda ORAM_PF1 (3)x3 @ dk.000*.054-062 850e sta PF1_ff (3)x3 @ dk.000*.063-071 *** a5d5 lda ORAM_PF2 (3)x3 @ dk.000*.072-080 850f sta PF2_ff (3)x3 @ dk.000*.081-089 *** --------------------------------------------------------------- DK WORK 3/17 - Preloads for 2nd of 4 1LK TIA Updates. Color Clocks: 138 x192/4 = 138 x48 = 6,624 ROM Bytes: 30 --------------------------------------------------------------- Preload Player Graphics. 98 tya (2)x3 @ dk.000*.090-095 N.B. clc rather than sec. 18 clc (2)x3 @ dk.000*.096-101 e587 sbc SRAM_P0_Y (3)x3 @ dk.000*.102-110 c5a7 cmp CRAM_P0_HEIGHT (3)x3 @ dk.000*.111-119 aa tax (2)x3 @ dk.000*.120-125 a900 lda #$00 (2)x3 @ dk.000*.126-131 e900 sbc #$00 (2)x3 @ dk.000*.132-137 35a9 and CRAM_GRP0_ROWS,X (4)x3 @ dk.000*.138-149 85d2 sta ORAM_GRP0 (3)x3 @ dk.000*.150-158 98 tya (2)x3 @ dk.000*.159-164 N.B. clc rather than sec. 18 clc (2)x3 @ dk.000*.165-170 e589 sbc SRAM_P1_Y (3)x3 @ dk.000*.171-179 c5b3 cmp CRAM_P1_HEIGHT (3)x3 @ dk.000*.180-188 aa tax (2)x3 @ dk.000*.189-194 a900 lda #$00 (2)x3 @ dk.000*.195-200 e900 sbc #$00 (2)x3 @ dk.000*.201-206 35b5 and CRAM_GRP1_ROWS,X (4)x3 @ dk.000*.207-218 a6d2 ldx ORAM_GRP0 (3)x3 @ dk.000*.219-227 The WIP source is attached to this post: https://forums.atariage.com/topic/336371-hello-2600-homebrewers/?do=findComment&comment=5103369 Quote Link to comment Share on other sites More sharing options...
Ecernosoft Posted August 18, 2022 Author Share Posted August 18, 2022 15 hours ago, The Brew that is True said: In my experimental WIP I'm using a single-scanline resolution kernel for the Player sprites (spliced with a 4LK for the PF and BL). Here's an excerpt: --------------------------------------------------------------- DK WORK 1/17 - 1LK TIA Updates - 1st of 4. Color Clocks: 27 x192/4 = 27 x48 = 1,296 ROM Bytes: 6 --------------------------------------------------------------- Update TIA Player Graphics registers. N.B. Assumes preloaded A register. 851c sta GRP1_ff (3)x3 @ dk.000*.000-008 *** a5d2 lda ORAM_GRP0 (3)x3 @ dk.000*.009-017 851b sta GRP0_ff (3)x3 @ dk.000*.018-026 *** --------------------------------------------------------------- DK WORK 2/17 - 4LK TIA Updates. Color Clocks: 63 x192/4 = 63 x48 = 3,024 ROM Bytes: 14 --------------------------------------------------------------- Update TIA PF Graphics and Ball Enable registers. TODO This is temporary test code. a5d3 lda ORAM_PF0_BL (3)x3 @ dk.000*.027-035 850d sta PF0_f0 (3)x3 @ dk.000*.036-044 *** 851f sta ENABL_02 (3)x3 @ dk.000*.045-053 *** a5d4 lda ORAM_PF1 (3)x3 @ dk.000*.054-062 850e sta PF1_ff (3)x3 @ dk.000*.063-071 *** a5d5 lda ORAM_PF2 (3)x3 @ dk.000*.072-080 850f sta PF2_ff (3)x3 @ dk.000*.081-089 *** --------------------------------------------------------------- DK WORK 3/17 - Preloads for 2nd of 4 1LK TIA Updates. Color Clocks: 138 x192/4 = 138 x48 = 6,624 ROM Bytes: 30 --------------------------------------------------------------- Preload Player Graphics. 98 tya (2)x3 @ dk.000*.090-095 N.B. clc rather than sec. 18 clc (2)x3 @ dk.000*.096-101 e587 sbc SRAM_P0_Y (3)x3 @ dk.000*.102-110 c5a7 cmp CRAM_P0_HEIGHT (3)x3 @ dk.000*.111-119 aa tax (2)x3 @ dk.000*.120-125 a900 lda #$00 (2)x3 @ dk.000*.126-131 e900 sbc #$00 (2)x3 @ dk.000*.132-137 35a9 and CRAM_GRP0_ROWS,X (4)x3 @ dk.000*.138-149 85d2 sta ORAM_GRP0 (3)x3 @ dk.000*.150-158 98 tya (2)x3 @ dk.000*.159-164 N.B. clc rather than sec. 18 clc (2)x3 @ dk.000*.165-170 e589 sbc SRAM_P1_Y (3)x3 @ dk.000*.171-179 c5b3 cmp CRAM_P1_HEIGHT (3)x3 @ dk.000*.180-188 aa tax (2)x3 @ dk.000*.189-194 a900 lda #$00 (2)x3 @ dk.000*.195-200 e900 sbc #$00 (2)x3 @ dk.000*.201-206 35b5 and CRAM_GRP1_ROWS,X (4)x3 @ dk.000*.207-218 a6d2 ldx ORAM_GRP0 (3)x3 @ dk.000*.219-227 The WIP source is attached to this post: https://forums.atariage.com/topic/336371-hello-2600-homebrewers/?do=findComment&comment=5103369 Does this use DCP? I said I wanted something DCPless, but if this is it, then yay! Quote Link to comment Share on other sites More sharing options...
The Brew that is True Posted August 18, 2022 Share Posted August 18, 2022 1 minute ago, Ecernosoft said: Does this use DCP? I said I wanted something DCPless, but if this is it, then yay! It does not use DCP, this is plain vanilla 4K. Quote Link to comment Share on other sites More sharing options...
Ecernosoft Posted August 18, 2022 Author Share Posted August 18, 2022 3 hours ago, The Brew that is True said: It does not use DCP, this is plain vanilla 4K. Yay! Quote Link to comment Share on other sites More sharing options...
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