Deadline for writes to WSYNC

[Eagle]

I’m looking for any information about Wsync for A7800

Atari xl/xe using Wsync as well and is well documented. 

Altira hardware manual saying:

 

Quote

Deadline for writes to WSYNC
Writes to WSYNC up to cycle 103 wait until the start of horizontal blank on the current scan line. A write to cycle 104 or later is too late and causes a wait until the start of horizontal blank on the next scan line.

But I can’t find any information about A7800 Wsync

Below picture is showing that right border is starting at 413 Maria cycle (413/4=103.25 CPU cycle)

I’m just guessing, if anyone know more please let me know

Thanks 

 

 

[+splendidnut]

Probably not that useful, but @RevEng experimented with this a bit (both Maria and TIA WSYNC registers):

 

 

 

[Trebor]

In addition to the above post, the below has been gathered, but will leave it to the experts to verify and/or clarify:

 

"WSYNC (Wait for Sync) is something inherited from the 2600. Writing to WSYNC halts the CPU until the beginning of the HBlank period between visible lines of the display. That means you can force the system to wait a number of lines for some basic 2600-like raster effects, but the downside is that you're wasting CPU time just counting lines."

SOURCE: https://forums.atariage.com/topic/331792-wizzy-on-the-7800/?do=findComment&comment=5025441

 

 

"There are a couple things to note about using such WSYNC tricks on the 7800, though:

-1- Although WSYNC on the 2600 is pixel-perfect, on the 7800 it is not. Because 6507 cycles may take 2 or 3 color clocks, there is a clock worth of jitter when the 6507 comes out of WSYNC. It would have been nice if MARIA would throw in a 3-chroma cycle if needed to even things out, but it doesn't.

-2- Hitting a color register mid-line will cause one pixel to appear 1.5 chroma clocks wide and the next pixel to appear 0.5 chroma clocks wide"

SOURCE: https://forums.atariage.com/topic/164265-wsync-strobe-on-a-7800/?do=findComment&comment=2029150

 

 

"One other item - WSYNC is not compatible with DLI. My first 7800 apps would STA WSYNC then test MSTAT for VBI. But then I figured out that STA WSYNC halts the 6502 so the DLI doesn't kick in as early. Additionally I think MSTAT is later than necessary. So I started using the DLI to flag the end of the frame and just have the mainline test for the flag without WSYNC."

SOURCE: https://forums.atariage.com/topic/164265-wsync-strobe-on-a-7800/?do=findComment&comment=2029600

 

 

"If you're hitting WSYNC near the end of the screen, you might roll that back a bit. It's been reported that WSYNC can mess up display interrupts, and there's one at the end of the visible screen in 7800basic."

SOURCE: https://forums.atariage.com/topic/256466-spire-of-the-ancients-wip/?do=findComment&comment=4201327

 

 

"I usually advised against mixing STA WSYNC and DLI as STA WSYNC pauses the CPU, which may cause it to miss the DLI interrupt (or at least delay it to the start of the next line)."

SOURCE: https://forums.atariage.com/topic/212970-need-to-reduce-the-cpu-time-this-routine-takes-help/?do=findComment&comment=2768598

 

 

"STA WSYNC which is similar to the 2600 version - the CPU pauses until the start of the next line. You get 7 CPU cycles before DMA HALTs the processor. (Enough time to update a MARIA register or two.)"

SOURCE: https://forums.atariage.com/topic/96543-my-unofficial-sally-questions-thread/?do=findComment&comment=1174302

 

 

"STA WSYNC writes a byte to a memory address used by MARIA which causes it to halt the 6502 until the start of the next line. And yes, although the assembler will do a certain amount of work for you (turning labels in to addresses, instructions into binary values, etc) you, as the programmer, are responsible for most of the work."

SOURCE: https://forums.atariage.com/topic/168633-system-to-program-a-7800-gamehow-to-go-about/?do=findComment&comment=2090666

 

 

"Note: don't use WSYNC outside of the DLI, if you have a DLI."

SOURCE: https://forums.atariage.com/topic/166625-reading-paddles-and-driving-controllers/?do=findComment&comment=2070606

 

 

"The only time I use WSYNC outside a DLI is for PAL/NTSC detection."

SOURCE: https://forums.atariage.com/topic/166625-reading-paddles-and-driving-controllers/?do=findComment&comment=2070777

[Eagle]

Thanks. I saw them all

But good to have them in one place. 
I started making tech demo for new cart. 
Changing Maria banks every zone plus playing sample on Covox didn’t go well  

I will try with @rj1307 do some tests because I have more questions than answers. 

[mono]

I wrote simple code to test where WSYNC releases CPU to go.

On the screen we can see two strips - red and green separated by black one.

The code is as following:

        lda #$00        ;black
        ldx #$33        ;red
        ldy #$CA        ;green

?loop   sta WSYNC

        stx BACKGRND
        jsr wait40
        sta BACKGRND

        sty BACKGRND
        jsr wait40
        sta BACKGRND

        jmp ?loop

wait40                  ;6
        bit $FFFF       ;4
        bit $FFFF       ;4
        bit $FFFF       ;4
        bit $FFFF       ;4
        bit $FFFF       ;4
        bit $FFFF       ;4
        bit $FFFF       ;4
        rts             ;6

We have got sequence of operations:

1. Stop CPU by store WSYNC.

2. Set red background - it takes 4 CPU cycles.

3. Wait 40 CPU cycles.

4. Set black background - it takes 4 CPU cycles.

5. Set green background - it takes 4 CPU cycles.

6. Wait 40 CPU cycles.

7. Set black background - it takes 4 CPU cycles.

On the top of the screen we can see 40 characters with narrow line at the left side of character

10000000

We know where the screen starts in the scanline (67th px of the scanline), we can calculate how many MARIA cycles take 40 CPU cycles (green and red stripes - 21.5 characters by 4 pixels = 86 px), we can calculate how many MARIA cycles takes one STA/STX/STY instruction (1.5 characters * 4 px = 6 px), we can see where is the right border of the red stripe (7.5 characters * 4 px = 30 px), so we can infer where CPU starts after STA WSYNC.

Based on information at http://7800.8bitdev.org/index.php/7800_Software_Guide#APPENDIX_4:_FRAME_TIMING it looks that after storing WSYNC the CPU is released at the beginning of scanline - probably at 5th pixel (67 px + 30 px - 86 px - 6 px = 5 px).

1 px is one pixel of 160 mode.

 

Edit: It's screenshot taken from A7800 emulator.

wsync.asx wsync.a78

Edited August 23, 2022 by mono
160 mode pixels calculations