Could ColecoVision's 8K RAM space be utilized

[+mytek]

1 hour ago, chart45 said:

i always share my stuff cause im doing it for fun and learning.

I feel the same way. If you go to my AtariBits website (link in signature), you'll see quite a few of my shared projects complete with schematics, BOMs, Firmware, and Gerbers. Every project is a learning experience for me.

[massiverobot]

17 hours ago, mytek said:

Even though the current chip count is lower than the Atari version, and there are fewer large chips to deal with, the cartridge is going to eat up that space pretty quickly. I'm trying to keep the profile low like the non-cart version of the 576NUC+, so it will end up being a top loader instead of a side loading cartridge. The plan is to make it fit the existing case STLs, with only minor changes, and probably have the lid take on some of the look of a real CV.   EDIT: It'll be a low profile when there is no cart inserted -- making it good for transport.

 

Ok, however, with FujiNet support already done (I'm imaging you do a ADAM-Net connection for a daughter board) I wonder what need is there for Carts? Every game is already available via TNFS / FujiNet and if you only support carts- well, then, you need to already own the carts. Maybe CV people already do own them all?

 

[+mytek]

7 minutes ago, massiverobot said:

Ok, however, with FujiNet support already done (I'm imaging you do a ADAM-Net connection for a daughter board) I wonder what need is there for Carts? Every game is already available via TNFS / FujiNet and if you only support carts- well, then, you need to already own the carts. Maybe CV people already do own them all?

I'm actually aiming this at supporting the AtariMax Ultimate SD Cart (or iffor someone that already has a physical cart collection). Really looking for fast loading which the SD Cart does very well, whereas FujiNet is kinda slow in comparison. I will try to squeeze in the expansion port for maybe a future FujiNet interface, although if it happens, it'll be a pin header.

[+mytek]

@chart45 can you verify where connection 1 and 2 go to?

 

 

Thanks

[chart45]

8 minutes ago, mytek said:

@chart45 can you verify where connection 1 and 2 go to?

 

 

Thanks

 

Edited September 20, 2022 by chart45

[+mytek]

@chart45 I see it in the thumbnail image, but for some odd reason when I click on it, the bottom of the image gets cut off. Unfortunately the small image is too tiny for me to accurately see what's connected and what the label says. Is it possible for you to crop that lower part and then post just that portion?

[chart45]

i dont know why the png is so bad when i post but here the file... maybe someone will be able to post a good picture of it.. its how i did but there is probably a better way  or better ic i could have used. 

ttlsgm.rar

Edited September 20, 2022 by chart45

[+mytek]

I was able to work from the last image you uploaded, and I did some creative changes before I head into learning WinCUPL for creating a JED file to use in a PLD.

 

So here's what I got...

 

Version 2

This one changed to a single 3-input AND gate (LS11) in place of the former two 2-input AND gates for the $2000-$7FFF select. Also changed to LS02 NOR gates where it was formally OR gates with additional LS04 INVERTERS on the outputs. Did away with two more LS04 gates by using NOT (/Q) outputs of LSS74 flip-flops.

 

 

Version 3

Went back to dual 2-input AND gates, but used the one left over LS02 NOR gate to eliminate the last LS04 INVERTER. When compared to the first iteration shared by @chart45 , this one requires one less chip (LS04).

 

EDIT: Corrected one of the labeled output wires.

EDIT2: I'm approaching this from an internal aspect and not something hanging off the expansion port, hence the reason you don't see the 74LS138 decoders which already exist.

 

15 inputs and 5 outputs = 20 pins required on the PLD, so it looks like a ATF22V10C-15PU should do the trick.

 

Now for the part I don't like, learning a new program

 

 

[chart45]

11 hours ago, mytek said:

I was able to work from the last image you uploaded, and I did some creative changes before I head into learning WinCUPL for creating a JED file to use in a PLD.

 

So here's what I got...

 

Version 2

This one changed to a single 3-input AND gate (LS11) in place of the former two 2-input AND gates for the $2000-$7FFF select. Also changed to LS02 NOR gates where it was formally OR gates with additional LS04 INVERTERS on the outputs. Did away with two more LS04 gates by using NOT (/Q) outputs of LSS74 flip-flops.

 

 

Version 3

Went back to dual 2-input AND gates, but used the one left over LS02 NOR gate to eliminate the last LS04 INVERTER. When compared to the first iteration shared by @chart45 , this one requires one less chip (LS04).

 

EDIT: Corrected one of the labeled output wires.

EDIT2: I'm approaching this from an internal aspect and not something hanging off the expansion port, hence the reason you don't see the 74LS138 decoders which already exist.

 

15 inputs and 5 outputs = 20 pins required on the PLD, so it looks like a ATF22V10C-15PU should do the trick.

 

Now for the part I don't like, learning a new program

 

 

here my code for banckswitching pcb

Name     megacart ;
PartNo   00 ;
Date     2021-12-11 ;
Revision 01 ;
Designer Engineer ;
Company  .... ;
Assembly None ;
Location  ;
Device   G20V8A ;

/* *************** INPUT PINS *********************/
PIN   1   =    CLK;                     /*  Register Clock      */
PIN   2   =    A8;                      /*  Address line A8     */
PIN   3   =    A7;                      /*  Address line A7     */
PIN   4   =    A6;                      /*  Address line A6     */
PIN   5   =    A5;                      /*  Address line A5     */
PIN   6   =    A4;                      /*  Address line A4     */
PIN   7   =    A3;                      /*  Address line A3     */
PIN   8   =    A2;                      /*  Address line A2     */
PIN   9   =    A1;                      /*  Address line A1     */
PIN   10  =    A0;                      /*  Address line A0     */  
PIN   11  =    LS21;                    /*  A9.....A12 = 1      */
PIN   13  =    OE;                      /*  Output Enable in    */
PIN   14  =    C0;                      /*  En_C0 line          */
PIN   23  =    E0;                      /*  En_E0 line          */

/* *************** OUTPUT PINS *********************/
PIN   15  =   E;                         /*  Output Enable           */
PIN   16  =   A14;                       /* Registered Output A14    */
PIN   17  =   A15;                       /* Registered Output A15    */
PIN   18  =   A16;                       /* Registered Output A16    */
PIN   19  =   A17;                       /* Registered Output A17    */
PIN   20  =   A18;                       /* Registered Output A18    */
PIN   21  =   A19;                       /* Registered Output A19    */
PIN   22  =   L1 ;                       /* Output to Clock          */

A14.D = A0;
A15.D = A1;
A16.D = A2;
A17.D = A3;
A18.D = A4;
A19.D = A5;
L1 = A6 & A7 & A8 & LS21 & C0 & !E0;
E = E0 & C0;

 

again i learned from google so expert probably have a way better code

 

[+mytek]

4 minutes ago, chart45 said:

here my code for banckswitching pcb

Thanks

 

-------

 

I screwed up on my reinterpretation of your SGM logic when I assumed that the 74LS138 decoders on your schematic mirrored the internal ones. IC7 (the top decoder) does not. So I would either need to pull that inside the PLD or just have an external LS138 connected as you showed. Got some thinking to do

[chart45]

i think you will need a cpld like an atf1502 or xilinx xc9536 to make it .. but im really not good at this stuff im still at the low level logic so i still use 74xx easy to test on bread board..  i need more spare time to learn vhdl.. 

[+mytek]

1 hour ago, chart45 said:

i think you will need a cpld like an atf1502 or xilinx xc9536 to make it .. but im really not good at this stuff im still at the low level logic so i still use 74xx easy to test on bread board..  i need more spare time to learn vhdl.. 

Yeah you and me both are probably in the early learning stages on that aspect. So I'm not sure if the ATF22V10 PLD has enough internal logic to pull it off, but if it does this may work for my project...

 

 

It'll need a total of 21 pins on the PLD, so that'll work with one pin to spare on the ATF22V10. If this were done in 74xx series logic, there is now a need for one additional 74LS32 chip, since I show five individual OR gates in this diagram.

[+mytek]

Well after much head scratching and sore eyeballs I found a way to get rid of that 5th OR gate and replace it with the extra gates that were already available. It's looking simpler and simpler as I keep tweaking with it. Of course @chart45 gets the credit for coming up with the original circuit, which would have taken me ages to get to this point if I had started from scratch.

 

SGM_Logic_Decode_V5.pdf

 

 

I've also been trying to figure out how to do this in a PLD, but quite frankly I don't think I'm cut out for that. So this led me back to the discrete logic circuit with the goal of getting further IC reduction. So I guess the next thing will be to test this in a bread board fashion glommed onto my real Colecovision.

[+mytek]

15 hours ago, mytek said:

I've also been trying to figure out how to do this in a PLD, but quite frankly I don't think I'm cut out for that.

Well perhaps I am. I kinda made a break through last night, and finally got a handle on how this works by coding for the logic in a small section of the schematic.

 

 

I then flashed a ATF22V10 PLD chip and powered it up while exercising the inputs, and watching the activity of the outputs. It worked 👍

 

Of course I have much more coding to do in order to capture the entire circuit, But I think I've gotten the concept of how to do it now. There's also a truth table aspect which I believe can be used to mirror a 74LS138 decoder's logic, and I believe I can also make use of the CLK input pin (pin-1) on the PLD to directly divide the 3.58Mhz CPU clock for use by the AY sound chip. So I think this will be doable

 

For development, I'm using WinCUPL which is available for free from Microchip. And I'm running the latest software for the TL866II Plus Programmer which will flash these PLD chips.

 

BTW, the ! specifies a NOT condition (or in other words inverts the result), # = OR, & = AND.

[chart45]

! is not 1 

.D to set in flip flop 

but i dont.know how to use the d flip flop to split the 3.58mhz for the ay chip.. 

i didnt look at the 22v10 but on the 20v8b clk trigger all the flip flop at the same time if i remember right.. i had hard time to find stuff for programming gal..  

Edited September 22, 2022 by chart45

[+mytek]

1 hour ago, chart45 said:

on the 20v8b clk trigger all the flip flop at the same time if i remember right

Yes it does, but the flip flop on each output goes through a MUX and you can opt to use it or not. I still have to put this in play myself (baby steps), but here's a good video showing how the built-in flip flops are implemented. You can see almost immediately in the video's cover image how the two MUXs allow for bypassing around the flip flop. So in theory you could feed the CLK input the 3.58Mhz, and then configure just one flip flop to have the /Q feed the D and send the Q output of what is now a frequency divider to the output pin of the PLD. Meanwhile all the other output flip flops can be bypassed with the MUX, thus leaving them free to use for other logic.

 

Edit: any additional flip flops that are not to be clocked at 3.58Mhz will need to be created in code.

 

 

[chart45]

nice video i wish i had found this one when i did my bankswitching pcb .i  will watch it  again when i get home. 

[+mytek]

On 9/22/2022 at 1:42 PM, chart45 said:

nice video i wish i had found this one when i did my bank switching pcb .i  will watch it  again when i get home. 

Yep I thought it was a good one as well.

 

------------

 

On a different subject, but one that I covered earlier in this topic about a method of extracting S-Video from the TMS via the LM1889 color encoder/modulator chip...

 

I've decided to break this out as a separate project and make a board that will take the place of the existing RF Modulator. It'll be designed to use the existing 8-pin header location, although it'll get a new female header installed in it's place. The idea will be to have a single board that other than the desoldering of the original modulator from the CV motherboard, is going to be plug 'n' play.

 

Where the RF output used to be, there will now be a fully buffered and gain adjusted audio output RCA jack. Next to that where the RF switch used to be, it'll get an industry standard Mini-DIN S-Video jack (will require using a step drill to make a larger round hole in the plastic case). And finally next to that will be a fully buffered composite video output RCA jack (will need a round hole added in the case -- use step drill). A threaded standoff will get used in place of the original plastic do-hickey to add rigidity to the mounting. And all of the jacks are to be right-angle PCB soldered types, so absolutely no wiring required (this is something that always annoyed me about other solutions).

 

Here's where the design is at thus far...

EDIT: The design in this schematic isn't quite right, and has since been improved. There is also a new topic that was started on this specific video upgrade where I'll be adding updated information and schematics.

 

I call it the EAV, which simply stands for Enhanced Audio Video.

 

I'll start working on a PCB layout early next week, and should have something to test in a couple of weeks.

 

My reason for doing this is to use it on my own Colecovision unit that I already stripped out the RF modulator. I figure this will be a nice neat replacement for something that I'll never use (RF). If I like how it works, the PCB gerber files will be uploaded in this forum for anyone else that wishes to make one for themselves. When and if that happens, I'll start a new topic dedicated to this board.

[+mytek]

I know, I know, so many posts and so many iterations in my SGM journey

 

Well guess what, I am taking yet another stab at the SGM decoding circuit. Think of it like you are on this journey with me as I learn about what minimally will pass for full SGM decoding from an internal perspective. Since this will not be hanging off the expansion bus in my proposed mini CV project, it has required a different approach. So in other words I ripped up what I had done previously and essentially started completely over, thanks in large part to the information I found HERE and HERE.

 

And because I was able to share unused aspects of existing chips on my Main Board design, I am now down to five chips to do all the required decoding and interface to the 32K SRAM and the AY-3-8910 sound chip.

 

So here's Version 6:

SGM_Logic_Decode_V6.pdf

 

[marauder666]

21 hours ago, mytek said:

Yep I thought it was a good one as well.

 

------------

 

On a different subject, but one that I covered earlier in this topic about a method of extracting S-Video from the TMS via the LM1889 color encoder/modulator chip...

 

I've decided to break this out as a separate project and make a board that will take the place of the existing RF Modulator. It'll be designed to use the existing 8-pin header location, although it'll get a new female header installed in it's place. The idea will be to have a single board that other than the desoldering of the original modulator from the CV motherboard, is going to be plug 'n' play.

 

Where the RF output used to be, there will now be a fully buffered and gain adjusted audio output RCA jack. Next to that where the RF switch used to be, it'll get an industry standard Mini-DIN S-Video jack (will require using a step drill to make a larger round hole in the plastic case). And finally next to that will be a fully buffered composite video output RCA jack (will need a round hole added in the case -- use step drill). A threaded standoff will get used in place of the original plastic do-hickey to add rigidity to the mounting. And all of the jacks are to be right-angle PCB soldered types, so absolutely no wiring required (this is something that always annoyed me about other solutions).

 

Here's where the design is at thus far...

I call it the EAV, which simply stands for Enhanced Audio Video.

 

I'll start working on a PCB layout early next week, and should have something to test in a couple of weeks.

 

My reason for doing this is to use it on my own Colecovision unit that I already stripped out the RF modulator. I figure this will be a nice neat replacement for something that I'll never use (RF). If I like how it works, the PCB gerber files will be uploaded in this forum for anyone else that wishes to make one for themselves. When and if that happens, I'll start a new topic dedicated to this board.

Hopefully it works well with minimal jailbars.  If it does i’ll get one built to replace my mod.

i did a s-video out and its pretty good, but has jailbars especially visible on the blue skill screens.

 

[+mytek]

1 hour ago, marauder666 said:

Hopefully it works well with minimal jailbars.  If it does i’ll get one built to replace my mod.

i did a s-video out and its pretty good, but has jailbars especially visible on the blue skill screens.

If I look real close, there are faint jail bars, but that greatly improved when I added the 12V to 5V linear voltage regulator for the analog circuitry's power. Having an independently regulated source of 5VDC just makes good sense, and I really wasn't left with a choice because only 12V is present on the 8-pin header. And due to it being a rats nest of wires on a plug-in protoboard, I think things will only get better when moving to a ground planed PCB. Fingers crossed

[marauder666]

I’ll add a separate 5v regulator to mine and see if it improves it.

[marauder666]

It didnt improve, worse in fact.  It was bodged in though, maybe the wires were picking up more interference than it usually does.

I'll wait for your results and PCB.

[+mytek]

4 hours ago, marauder666 said:

It didnt improve, worse in fact.  It was bodged in though, maybe the wires were picking up more interference than it usually does.

I'll wait for your results and PCB.

Sorry to hear that didn't help. I'd be interested to see an image of what your jail bars look like. Can you capture it in a photo of the blue start-up screen?

[marauder666]

On my ancient Sony BVM.

Here's a thread I posted when I got the machine a few months ago, some more pics.

Edited September 24, 2022 by marauder666