+llabnip Posted November 8, 2022 Share Posted November 8, 2022 So I'm working hard to clean up all of the cycle inaccuracies in my A7800DS emulator. It's based on ProSystem and so it's inherited some cycle problems. It looks like a lot of solid confirmed information has surfaced since the initial ProSystem emulation was developed - and I've been reading as much of it as I can to try and understand things. I've got 90% of the timing stuff cleaned up - and just about everything is running pretty damn close to perfect but there is something I'd like to check: Does the highlighted statement of "no DMA penalty" mean that we don't incur the 3/6/9 cycle penalty if that fetch results in a DMA hole? Right now A7800DS (and just about every ProSystem-based emulator) doesn't care if it's a DMA hole or a real data fetch... so the cycle cost is always counted. 3 Quote Link to comment Share on other sites More sharing options...
RevEng Posted November 8, 2022 Share Posted November 8, 2022 19 minutes ago, llabnip said: Does the highlighted statement of "no DMA penalty" mean that we don't incur the 3/6/9 cycle penalty if that fetch results in a DMA hole? Right now A7800DS (and just about every ProSystem-based emulator) doesn't care if it's a DMA hole or a real data fetch... so the cycle cost is always counted. Correct, and this is how I've implemented it in A7800. The author of the 7800 core in the BizHawk emulator had some conflicting advice. I haven't been able to make that work with accuracy, so I'm not entirely sure there. 1 Quote Link to comment Share on other sites More sharing options...
+llabnip Posted November 8, 2022 Author Share Posted November 8, 2022 Super interesting read in your referenced thread. Man... this thing is like peeling an onion. Unfortunately, I'm really up against my CPU limit. Having a 67MHz ARM target is rather limiting (which is a challenge I've enjoyed!) but the nuances of the timing are starting to have an appreciable cost and I may back off to something a bit more 'simple' while maintaining 'reasonable' accuracy. In the end, users want to blast rocks and destroy robots - and it won't do me any good to say "yeah, it's a little slow but it's cycle accurate!" 1 Quote Link to comment Share on other sites More sharing options...
RevEng Posted November 8, 2022 Share Posted November 8, 2022 You've done a fantastic job of optimising! Reading through your source recently, I was struck a few times about how clever you were about minimising conditional logic. Even PC based emulation does that same trade-off. We could be much more accurate if everything was emulated gates, but then everybody would have to play a very boring slideshow. 4 Quote Link to comment Share on other sites More sharing options...
+llabnip Posted November 8, 2022 Author Share Posted November 8, 2022 (edited) Thanks again @RevEng So far in my early tests, things are working well with the streamlined and hopefully more accurate timing. One notable issues is Xevious. I have to add an extra 16 Maria cycles to prevent the horizontal line from appearing. It's easy enough to have a fudge factor for some games... but it's perplexing that I need more Maria cycle compensation to make that one run right. The other game is b*nQ which needs 3 fewer Maria cycles added (subtracted) to prevent small glitches on the title screen. Which makes me think I'm still not quite there. But busy hands are happy hands Edit: in jettisoning some old ProSystem stuff to clean it up, I removed the compensation for a DLI. That compensation fixes Xevious. So now it's just the odd game here or there that requires a couple of cycle tweak. Better. Edited November 8, 2022 by llabnip 3 Quote Link to comment Share on other sites More sharing options...
Eagle Posted November 8, 2022 Share Posted November 8, 2022 (edited) Hi @llabnip, I did some timing tests few months ago (for wsync and vblank timing) I'm planning to do some Maria test as well (dma, holey, dli) If you are interested I can attach later. Below timing for this short code. I'm also attaching DSLogic file (you can view under DsView, it's free) Edit: Ignore spikes 10-30ns loop_konsol jsr WaitVBLANK inx jmp loop_konsol WaitVBLANK: WaitVBoff: stx $40 bit MSTAT bmi WaitVBoff WaitVBon: stx $41 bit MSTAT bpl WaitVBon sta $42 sta Wsync stx BACKGRND rts DSLogic-la-220831-071756.dsl Edited November 8, 2022 by Eagle 4 Quote Link to comment Share on other sites More sharing options...
Ecernosoft Posted November 13, 2022 Share Posted November 13, 2022 On 11/8/2022 at 11:08 AM, RevEng said: You've done a fantastic job of optimising! Reading through your source recently, I was struck a few times about how clever you were about minimising conditional logic. Even PC based emulation does that same trade-off. We could be much more accurate if everything was emulated gates, but then everybody would have to play a very boring slideshow. I agree!! For the DS, it’s impressive! Quote Link to comment Share on other sites More sharing options...
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