+DZ-Jay Posted December 15, 2022 Share Posted December 15, 2022 8 hours ago, tschak909 said: What would using SSH via the #FujiNet on the #Intellivision look like? Like this. Some of the crazy things possible with our codebase, but we need hardware engineering help to work out the bus interface. Please consider joining our discord, if you can help: https://discord.gg/7MfFTvD #retrogaming #retrocomputing I tried to join the Discord channel, but when I click on "Accept Invitation," I get, "Safari cannot open the page because the address is invalid." dZ. Quote Link to comment Share on other sites More sharing options...
tschak909 Posted December 15, 2022 Author Share Posted December 15, 2022 6 hours ago, JohnPCAE said: I'm still trying to understand. Does FujiNet have existing hardware that the Inty could talk to, or is it just a software stack? I've noted that you mentioned that you have cross-platform software, but we don't have a C compiler for the CP-1600 CPU as far as I know. We have IntyBasic which is a cross-compiler and we have CP-1600 assembly. I can explain: #FujiNet is built on: * Firmware for an ESP32 that provides the bulk of the stack for all sorts of devices ** Virtual software loading ** Virtual printing ** Protocol offloaded networking * A board containing an ESP32 and appropriate interfacing for the target system. * Host software that talks to the board to implement the host side of various functions. For the firmware, we split things up so that we have a concept of: * Busses (the target system and the protocols they need to talk, even if they are bespoke) Atari SIO, RS232, AdamNet, Apple IWM (SmartPort), ComLynx, etc. * Devices (the individual devices that can be implemented, disk, printer, network, modem, etc.) * Media (just as implied) And the network device divides this even further by adding protocol adapters: * HTTP/S * FTP * TNFS * TCP * UDP * SSH * TELNET and so on. So e.g. the Intellivision could immediately use the software loading, and networking devices, even without a keyboard. I did the SSH client as an example that no matter which target is built, the support for various protocols is there and can be used, so e.g. a game could establish an SSH connection if wanted. What we need help on, is to come up with a workable bus interface that I could write the bus firmware for, and the rest of the stack would immediately be usable, even in IntyBASIC. Not having a C compiler doesn't matter, because...well...the important part of the system is to get the firmware to bus implemention working, then I can write the firmware, and example software to use it. -Thom 1 Quote Link to comment Share on other sites More sharing options...
tschak909 Posted December 15, 2022 Author Share Posted December 15, 2022 4 hours ago, DZ-Jay said: I tried to join the Discord channel, but when I click on "Accept Invitation," I get, "Safari cannot open the page because the address is invalid." dZ. I smell ISP DNS shenanigans. Try this? https://discord.com/invite/7MfFTvD -Thom Quote Link to comment Share on other sites More sharing options...
JohnPCAE Posted December 16, 2022 Share Posted December 16, 2022 (edited) I put together some sample code for manipulating the ACC's parallel port. With this you can bit-bang the parallel port pins. Do you need me to build you an ACC unit so you have something to test with? I'm also attaching a PDF that describes the operation of the parallel port on a PC. It's what I followed when implementing it on the ACC. The ACC's parallel port is meant to operate like the port on a PC as closely as possible. The only deviation is that pin 17 is output-only in my implementation because I didn't have an IC pin available to read it. ; ACC registers ACC_REG_INDEX EQU $007E ACC_REG_VALUE EQU $007F ACC_REG_SIGNATURE EQU 0 ; read-only, always returns MAGIC_SIGNATURE (0x5EE5) ACC_REG_ENABLE EQU 1 ; .........ppppevm m = enable memory, v = enable video, e = sprite exclusion, ACC_REG_PALETTE_INDEX EQU 2 ; .......rrrrrrrrr 0 .. 511 allowed (256 palette colors, 2 registers per color) ACC_REG_PALETTE_VALUE EQU 3 ; bbbbbbbbaaaaaaaa two timeslice values (four timeslice values make up a single palette color) ACC_REG_STATUS_INFO EQU 4 ; r.......mmmmmmmm read-only. returns the number of times MSYNC went from low to high and whether the emulator is running. ACC_REG_CURSOR EQU 5 ; ......bceeeessss s = start scanline, e = end scanline, c = show cursor, b = enable cursor blink ACC_REG_CURSOR_POS EQU 6 ; yyyyyyyyxxxxxxxx y = row (0 .. 23), x = column (0 .. 39/79) ACC_REG_CHAR_SCANLINES EQU 7 ; ............ssss 1 .. 15 allowed ACC_REG_SCROLL_V EQU 8 ; ............vvvv 0 .. char. scanlines - 1, specifies starting character scan line ACC_REG_BUFFER_START EQU 9 ; dword location within video memory (4-byte granularity) ACC_REG_BUFFER_PITCH EQU 10 ; 1 .. 160 allowed. character-mode virtual screen pitch in characters. ACC_REG_SCREEN_MODE EQU 11 ; 0 .. SCREEN_MODE_MAX allowed (anything over the max is treated as the max) ACC_REG_GRAM_START EQU 12 ; the location within video memory (word granularity). Used only by text modes. ACC_REG_RESERVED EQU 13 ACC_REG_CYCLE_COUNT_LO EQU 14 ; read-only. low word of the raw bus cycle count ACC_REG_CYCLE_COUNT_HI EQU 15 ; read-only. high word of the raw bus cycle count ACC_REG_PARALLEL_DATA EQU 16 ; ........dddddddd bidirectional parallel port data register ACC_REG_PARALLEL_STATUS EQU 17 ; ........dddddddd same format as PC parallel port status register ACC_REG_PARALLEL_CONTROL EQU 18 ; ..........d.dddd same format as PC parallel port control register ACC_REG_START_PROCESSOR EQU 19 ; write an address here to tell the emulator to immediately start running at that location ACC_REG_EBCI EQU 20 ; read by emulated BEXT instruction ACC_REG_INT_VECTOR EQU 21 ; memory location used when triggering an interrupt with REG_INTERRUPT ACC_REG_INTERRUPT EQU 22 ; writing anything here triggers an interrupt in the emulator. does nothing if the emulator is halted. ACC_REG_R0 EQU 23 ; emulated CP-1600 register R0 ACC_REG_R1 EQU 24 ; emulated CP-1600 register R1 ACC_REG_R2 EQU 25 ; emulated CP-1600 register R2 ACC_REG_R3 EQU 26 ; emulated CP-1600 register R3 ACC_REG_R4 EQU 27 ; emulated CP-1600 register R4 ACC_REG_R5 EQU 28 ; emulated CP-1600 register R5 ACC_REG_R6 EQU 29 ; emulated CP-1600 register R6 ACC_REG_R7 EQU 30 ; emulated CP-1600 register R7 ACC_REG_FLAGS EQU 31 ; emulated CP-1600 flags ACC_BUFFER EQU $D000 ACC_ENABLE_ACCESS EQU 1 ACC_ENABLE_VIDEO EQU 2 ACC_ENABLE EQU 3 ACC_SIGNATURE EQU $5EE5 ; ------------------------------------------------------------- ; Returns whether the ACC (Advanced Console Component) is present ; ; Returns value in R0 ; 0 - not present ; 1 - present IsACCPresent PROC PSHR R5 PSHR R1 MVII #ACC_REG_SIGNATURE, R0 MVO R0, ACC_REG_INDEX MVII #ACC_REG_VALUE, R1 MVI@ R1, R1 CLRR R0 CMPI #ACC_SIGNATURE, R1 BNEQ @@ACCNotFound INCR R0 @@ACCNotFound: PULR R1 PULR R7 ENDP ; ------------------------------------------------------------- ; Writes to the parallel port data pins ; ; Data pins are pins 2-9 on the DB25 connector. ; ; R0 - The byte to output WriteParallelDataPort PROC PSHR R5 PSHR R1 MVII #ACC_REG_PARALLEL_DATA, R1 MVO R1, ACC_REG_INDEX MVO R0, ACC_REG_VALUE PULR R1 PULR R7 ENDP ; ------------------------------------------------------------- ; Reads from the parallel port data pins and returns it in R0 ; ; Data pins are pins 2-9 on the DB25 connector. ReadParallelDataPort PROC PSHR R5 MVII #ACC_REG_PARALLEL_DATA, R0 MVO R0, ACC_REG_INDEX MVI ACC_REG_VALUE, R0 PULR R7 ENDP ; ------------------------------------------------------------- ; Reads from the parallel port status pins and returns it in R0. ; Use this to read port pins 1, 10-16. ; ; Bit Name Inverted Port pin Type ; --------------------------------------------------- ; 0 Strobe Yes 1 Control ; 1 AutoLF Yes 14 Control ; 2 Init No 16 Control ; 3 Error No 15 Status ; 4 Select No 13 Status ; 5 Paper out No 12 Status ; 6 ACK No 10 Status ; 7 Busy Yes 11 Status ReadParallelStatusPort PROC PSHR R5 MVII #ACC_REG_PARALLEL_STATUS, R0 MVO R0, ACC_REG_INDEX MVI ACC_REG_VALUE, R0 PULR R7 ENDP ; ------------------------------------------------------------- ; Writes to the parallel port control port. Use this to output ; to control port pins 1, 14, 16, 17 and set whether data pins ; 2-9 are input or output. ; ; Bit Name Port pin ; -------------------------------- ; 0 Strobe 1 ; 1 AutoLF 14 ; 2 Init 16 ; 3 Select printer 17 ; 4 Reserved N/A ; 5 Data input N/A ; 6 Reserved N/A ; 7 Reserved N/A ; ; R0 - The byte to output WriteParallelControlPort PROC PSHR R5 PSHR R1 MVII #ACC_REG_PARALLEL_CONTROL, R1 MVO R1, ACC_REG_INDEX MVO R0, ACC_REG_VALUE PULR R1 PULR R7 ENDP ; ------------------------------------------------------------- ; Reads from the parallel port control port and returns it in R0. ; This cannot be used to read the state of port pins 1, 14, 16, ; and 17 (see status port) but it can be used to read what is ; being output to those pins as well as read the state of the ; Data input bit. ; ; Bit Name Port pin ; -------------------------------- ; 0 Strobe 1 ; 1 AutoLF 14 ; 2 Init 16 ; 3 Select printer 17 ; 4 Reserved N/A ; 5 Data input N/A ; 6 Reserved N/A ; 7 Reserved N/A ReadParallelControlPort PROC PSHR R5 MVII #ACC_REG_PARALLEL_CONTROL, R0 MVO R0, ACC_REG_INDEX MVI ACC_REG_VALUE, R0 PULR R7 ENDP ; ------------------------------------------------------------- ; Sets the parallel port data pins to output SetParallelDataOutput PROC PSHR R5 PSHR R0 MVII #ACC_REG_PARALLEL_CONTROL, R0 MVO R0, ACC_REG_INDEX MVI ACC_REG_VALUE, R0 ANDI #$00DF, R0 MVO R0, ACC_REG_VALUE PULR R0 PULR R7 ENDP ; ------------------------------------------------------------- ; Sets the parallel port data pins to input SetParallelDataInput PROC PSHR R5 PSHR R0 MVII #ACC_REG_PARALLEL_CONTROL, R0 MVO R0, ACC_REG_INDEX MVI ACC_REG_VALUE, R0 ANDI #$00DF, R0 XORI #$0020, R0 MVO R0, ACC_REG_VALUE PULR R0 PULR R7 ENDP parallel.pdf Edited December 16, 2022 by JohnPCAE Quote Link to comment Share on other sites More sharing options...
tschak909 Posted December 16, 2022 Author Share Posted December 16, 2022 12 hours ago, JohnPCAE said: I put together some sample code for manipulating the ACC's parallel port. With this you can bit-bang the parallel port pins. Do you need me to build you an ACC unit so you have something to test with? I'm also attaching a PDF that describes the operation of the parallel port on a PC. It's what I followed when implementing it on the ACC. The ACC's parallel port is meant to operate like the port on a PC as closely as possible. The only deviation is that pin 17 is output-only in my implementation because I didn't have an IC pin available to read it. ; ACC registers ACC_REG_INDEX EQU $007E ACC_REG_VALUE EQU $007F ACC_REG_SIGNATURE EQU 0 ; read-only, always returns MAGIC_SIGNATURE (0x5EE5) ACC_REG_ENABLE EQU 1 ; .........ppppevm m = enable memory, v = enable video, e = sprite exclusion, ACC_REG_PALETTE_INDEX EQU 2 ; .......rrrrrrrrr 0 .. 511 allowed (256 palette colors, 2 registers per color) ACC_REG_PALETTE_VALUE EQU 3 ; bbbbbbbbaaaaaaaa two timeslice values (four timeslice values make up a single palette color) ACC_REG_STATUS_INFO EQU 4 ; r.......mmmmmmmm read-only. returns the number of times MSYNC went from low to high and whether the emulator is running. ACC_REG_CURSOR EQU 5 ; ......bceeeessss s = start scanline, e = end scanline, c = show cursor, b = enable cursor blink ACC_REG_CURSOR_POS EQU 6 ; yyyyyyyyxxxxxxxx y = row (0 .. 23), x = column (0 .. 39/79) ACC_REG_CHAR_SCANLINES EQU 7 ; ............ssss 1 .. 15 allowed ACC_REG_SCROLL_V EQU 8 ; ............vvvv 0 .. char. scanlines - 1, specifies starting character scan line ACC_REG_BUFFER_START EQU 9 ; dword location within video memory (4-byte granularity) ACC_REG_BUFFER_PITCH EQU 10 ; 1 .. 160 allowed. character-mode virtual screen pitch in characters. ACC_REG_SCREEN_MODE EQU 11 ; 0 .. SCREEN_MODE_MAX allowed (anything over the max is treated as the max) ACC_REG_GRAM_START EQU 12 ; the location within video memory (word granularity). Used only by text modes. ACC_REG_RESERVED EQU 13 ACC_REG_CYCLE_COUNT_LO EQU 14 ; read-only. low word of the raw bus cycle count ACC_REG_CYCLE_COUNT_HI EQU 15 ; read-only. high word of the raw bus cycle count ACC_REG_PARALLEL_DATA EQU 16 ; ........dddddddd bidirectional parallel port data register ACC_REG_PARALLEL_STATUS EQU 17 ; ........dddddddd same format as PC parallel port status register ACC_REG_PARALLEL_CONTROL EQU 18 ; ..........d.dddd same format as PC parallel port control register ACC_REG_START_PROCESSOR EQU 19 ; write an address here to tell the emulator to immediately start running at that location ACC_REG_EBCI EQU 20 ; read by emulated BEXT instruction ACC_REG_INT_VECTOR EQU 21 ; memory location used when triggering an interrupt with REG_INTERRUPT ACC_REG_INTERRUPT EQU 22 ; writing anything here triggers an interrupt in the emulator. does nothing if the emulator is halted. ACC_REG_R0 EQU 23 ; emulated CP-1600 register R0 ACC_REG_R1 EQU 24 ; emulated CP-1600 register R1 ACC_REG_R2 EQU 25 ; emulated CP-1600 register R2 ACC_REG_R3 EQU 26 ; emulated CP-1600 register R3 ACC_REG_R4 EQU 27 ; emulated CP-1600 register R4 ACC_REG_R5 EQU 28 ; emulated CP-1600 register R5 ACC_REG_R6 EQU 29 ; emulated CP-1600 register R6 ACC_REG_R7 EQU 30 ; emulated CP-1600 register R7 ACC_REG_FLAGS EQU 31 ; emulated CP-1600 flags ACC_BUFFER EQU $D000 ACC_ENABLE_ACCESS EQU 1 ACC_ENABLE_VIDEO EQU 2 ACC_ENABLE EQU 3 ACC_SIGNATURE EQU $5EE5 ; ------------------------------------------------------------- ; Returns whether the ACC (Advanced Console Component) is present ; ; Returns value in R0 ; 0 - not present ; 1 - present IsACCPresent PROC PSHR R5 PSHR R1 MVII #ACC_REG_SIGNATURE, R0 MVO R0, ACC_REG_INDEX MVII #ACC_REG_VALUE, R1 MVI@ R1, R1 CLRR R0 CMPI #ACC_SIGNATURE, R1 BNEQ @@ACCNotFound INCR R0 @@ACCNotFound: PULR R1 PULR R7 ENDP ; ------------------------------------------------------------- ; Writes to the parallel port data pins ; ; Data pins are pins 2-9 on the DB25 connector. ; ; R0 - The byte to output WriteParallelDataPort PROC PSHR R5 PSHR R1 MVII #ACC_REG_PARALLEL_DATA, R1 MVO R1, ACC_REG_INDEX MVO R0, ACC_REG_VALUE PULR R1 PULR R7 ENDP ; ------------------------------------------------------------- ; Reads from the parallel port data pins and returns it in R0 ; ; Data pins are pins 2-9 on the DB25 connector. ReadParallelDataPort PROC PSHR R5 MVII #ACC_REG_PARALLEL_DATA, R0 MVO R0, ACC_REG_INDEX MVI ACC_REG_VALUE, R0 PULR R7 ENDP ; ------------------------------------------------------------- ; Reads from the parallel port status pins and returns it in R0. ; Use this to read port pins 1, 10-16. ; ; Bit Name Inverted Port pin Type ; --------------------------------------------------- ; 0 Strobe Yes 1 Control ; 1 AutoLF Yes 14 Control ; 2 Init No 16 Control ; 3 Error No 15 Status ; 4 Select No 13 Status ; 5 Paper out No 12 Status ; 6 ACK No 10 Status ; 7 Busy Yes 11 Status ReadParallelStatusPort PROC PSHR R5 MVII #ACC_REG_PARALLEL_STATUS, R0 MVO R0, ACC_REG_INDEX MVI ACC_REG_VALUE, R0 PULR R7 ENDP ; ------------------------------------------------------------- ; Writes to the parallel port control port. Use this to output ; to control port pins 1, 14, 16, 17 and set whether data pins ; 2-9 are input or output. ; ; Bit Name Port pin ; -------------------------------- ; 0 Strobe 1 ; 1 AutoLF 14 ; 2 Init 16 ; 3 Select printer 17 ; 4 Reserved N/A ; 5 Data input N/A ; 6 Reserved N/A ; 7 Reserved N/A ; ; R0 - The byte to output WriteParallelControlPort PROC PSHR R5 PSHR R1 MVII #ACC_REG_PARALLEL_CONTROL, R1 MVO R1, ACC_REG_INDEX MVO R0, ACC_REG_VALUE PULR R1 PULR R7 ENDP ; ------------------------------------------------------------- ; Reads from the parallel port control port and returns it in R0. ; This cannot be used to read the state of port pins 1, 14, 16, ; and 17 (see status port) but it can be used to read what is ; being output to those pins as well as read the state of the ; Data input bit. ; ; Bit Name Port pin ; -------------------------------- ; 0 Strobe 1 ; 1 AutoLF 14 ; 2 Init 16 ; 3 Select printer 17 ; 4 Reserved N/A ; 5 Data input N/A ; 6 Reserved N/A ; 7 Reserved N/A ReadParallelControlPort PROC PSHR R5 MVII #ACC_REG_PARALLEL_CONTROL, R0 MVO R0, ACC_REG_INDEX MVI ACC_REG_VALUE, R0 PULR R7 ENDP ; ------------------------------------------------------------- ; Sets the parallel port data pins to output SetParallelDataOutput PROC PSHR R5 PSHR R0 MVII #ACC_REG_PARALLEL_CONTROL, R0 MVO R0, ACC_REG_INDEX MVI ACC_REG_VALUE, R0 ANDI #$00DF, R0 MVO R0, ACC_REG_VALUE PULR R0 PULR R7 ENDP ; ------------------------------------------------------------- ; Sets the parallel port data pins to input SetParallelDataInput PROC PSHR R5 PSHR R0 MVII #ACC_REG_PARALLEL_CONTROL, R0 MVO R0, ACC_REG_INDEX MVI ACC_REG_VALUE, R0 ANDI #$00DF, R0 XORI #$0020, R0 MVO R0, ACC_REG_VALUE PULR R0 PULR R7 ENDP parallel.pdf 76.49 kB · 0 downloads Where does the parallel port sit in the memory map? -Thom Quote Link to comment Share on other sites More sharing options...
+DZ-Jay Posted December 16, 2022 Share Posted December 16, 2022 (edited) 13 hours ago, JohnPCAE said: I put together some sample code for manipulating the ACC's parallel port. With this you can bit-bang the parallel port pins. Do you need me to build you an ACC unit so you have something to test with? I'm also attaching a PDF that describes the operation of the parallel port on a PC. It's what I followed when implementing it on the ACC. The ACC's parallel port is meant to operate like the port on a PC as closely as possible. The only deviation is that pin 17 is output-only in my implementation because I didn't have an IC pin available to read it. ; ACC registers ACC_REG_INDEX EQU $007E ACC_REG_VALUE EQU $007F ACC_REG_SIGNATURE EQU 0 ; read-only, always returns MAGIC_SIGNATURE (0x5EE5) ACC_REG_ENABLE EQU 1 ; .........ppppevm m = enable memory, v = enable video, e = sprite exclusion, ACC_REG_PALETTE_INDEX EQU 2 ; .......rrrrrrrrr 0 .. 511 allowed (256 palette colors, 2 registers per color) ACC_REG_PALETTE_VALUE EQU 3 ; bbbbbbbbaaaaaaaa two timeslice values (four timeslice values make up a single palette color) ACC_REG_STATUS_INFO EQU 4 ; r.......mmmmmmmm read-only. returns the number of times MSYNC went from low to high and whether the emulator is running. ACC_REG_CURSOR EQU 5 ; ......bceeeessss s = start scanline, e = end scanline, c = show cursor, b = enable cursor blink ACC_REG_CURSOR_POS EQU 6 ; yyyyyyyyxxxxxxxx y = row (0 .. 23), x = column (0 .. 39/79) ACC_REG_CHAR_SCANLINES EQU 7 ; ............ssss 1 .. 15 allowed ACC_REG_SCROLL_V EQU 8 ; ............vvvv 0 .. char. scanlines - 1, specifies starting character scan line ACC_REG_BUFFER_START EQU 9 ; dword location within video memory (4-byte granularity) ACC_REG_BUFFER_PITCH EQU 10 ; 1 .. 160 allowed. character-mode virtual screen pitch in characters. ACC_REG_SCREEN_MODE EQU 11 ; 0 .. SCREEN_MODE_MAX allowed (anything over the max is treated as the max) ACC_REG_GRAM_START EQU 12 ; the location within video memory (word granularity). Used only by text modes. ACC_REG_RESERVED EQU 13 ACC_REG_CYCLE_COUNT_LO EQU 14 ; read-only. low word of the raw bus cycle count ACC_REG_CYCLE_COUNT_HI EQU 15 ; read-only. high word of the raw bus cycle count ACC_REG_PARALLEL_DATA EQU 16 ; ........dddddddd bidirectional parallel port data register ACC_REG_PARALLEL_STATUS EQU 17 ; ........dddddddd same format as PC parallel port status register ACC_REG_PARALLEL_CONTROL EQU 18 ; ..........d.dddd same format as PC parallel port control register ACC_REG_START_PROCESSOR EQU 19 ; write an address here to tell the emulator to immediately start running at that location ACC_REG_EBCI EQU 20 ; read by emulated BEXT instruction ACC_REG_INT_VECTOR EQU 21 ; memory location used when triggering an interrupt with REG_INTERRUPT ACC_REG_INTERRUPT EQU 22 ; writing anything here triggers an interrupt in the emulator. does nothing if the emulator is halted. ACC_REG_R0 EQU 23 ; emulated CP-1600 register R0 ACC_REG_R1 EQU 24 ; emulated CP-1600 register R1 ACC_REG_R2 EQU 25 ; emulated CP-1600 register R2 ACC_REG_R3 EQU 26 ; emulated CP-1600 register R3 ACC_REG_R4 EQU 27 ; emulated CP-1600 register R4 ACC_REG_R5 EQU 28 ; emulated CP-1600 register R5 ACC_REG_R6 EQU 29 ; emulated CP-1600 register R6 ACC_REG_R7 EQU 30 ; emulated CP-1600 register R7 ACC_REG_FLAGS EQU 31 ; emulated CP-1600 flags ACC_BUFFER EQU $D000 ACC_ENABLE_ACCESS EQU 1 ACC_ENABLE_VIDEO EQU 2 ACC_ENABLE EQU 3 ACC_SIGNATURE EQU $5EE5 ; ------------------------------------------------------------- ; Returns whether the ACC (Advanced Console Component) is present ; ; Returns value in R0 ; 0 - not present ; 1 - present IsACCPresent PROC PSHR R5 PSHR R1 MVII #ACC_REG_SIGNATURE, R0 MVO R0, ACC_REG_INDEX MVII #ACC_REG_VALUE, R1 MVI@ R1, R1 CLRR R0 CMPI #ACC_SIGNATURE, R1 BNEQ @@ACCNotFound INCR R0 @@ACCNotFound: PULR R1 PULR R7 ENDP ; ------------------------------------------------------------- ; Writes to the parallel port data pins ; ; Data pins are pins 2-9 on the DB25 connector. ; ; R0 - The byte to output WriteParallelDataPort PROC PSHR R5 PSHR R1 MVII #ACC_REG_PARALLEL_DATA, R1 MVO R1, ACC_REG_INDEX MVO R0, ACC_REG_VALUE PULR R1 PULR R7 ENDP ; ------------------------------------------------------------- ; Reads from the parallel port data pins and returns it in R0 ; ; Data pins are pins 2-9 on the DB25 connector. ReadParallelDataPort PROC PSHR R5 MVII #ACC_REG_PARALLEL_DATA, R0 MVO R0, ACC_REG_INDEX MVI ACC_REG_VALUE, R0 PULR R7 ENDP ; ------------------------------------------------------------- ; Reads from the parallel port status pins and returns it in R0. ; Use this to read port pins 1, 10-16. ; ; Bit Name Inverted Port pin Type ; --------------------------------------------------- ; 0 Strobe Yes 1 Control ; 1 AutoLF Yes 14 Control ; 2 Init No 16 Control ; 3 Error No 15 Status ; 4 Select No 13 Status ; 5 Paper out No 12 Status ; 6 ACK No 10 Status ; 7 Busy Yes 11 Status ReadParallelStatusPort PROC PSHR R5 MVII #ACC_REG_PARALLEL_STATUS, R0 MVO R0, ACC_REG_INDEX MVI ACC_REG_VALUE, R0 PULR R7 ENDP ; ------------------------------------------------------------- ; Writes to the parallel port control port. Use this to output ; to control port pins 1, 14, 16, 17 and set whether data pins ; 2-9 are input or output. ; ; Bit Name Port pin ; -------------------------------- ; 0 Strobe 1 ; 1 AutoLF 14 ; 2 Init 16 ; 3 Select printer 17 ; 4 Reserved N/A ; 5 Data input N/A ; 6 Reserved N/A ; 7 Reserved N/A ; ; R0 - The byte to output WriteParallelControlPort PROC PSHR R5 PSHR R1 MVII #ACC_REG_PARALLEL_CONTROL, R1 MVO R1, ACC_REG_INDEX MVO R0, ACC_REG_VALUE PULR R1 PULR R7 ENDP ; ------------------------------------------------------------- ; Reads from the parallel port control port and returns it in R0. ; This cannot be used to read the state of port pins 1, 14, 16, ; and 17 (see status port) but it can be used to read what is ; being output to those pins as well as read the state of the ; Data input bit. ; ; Bit Name Port pin ; -------------------------------- ; 0 Strobe 1 ; 1 AutoLF 14 ; 2 Init 16 ; 3 Select printer 17 ; 4 Reserved N/A ; 5 Data input N/A ; 6 Reserved N/A ; 7 Reserved N/A ReadParallelControlPort PROC PSHR R5 MVII #ACC_REG_PARALLEL_CONTROL, R0 MVO R0, ACC_REG_INDEX MVI ACC_REG_VALUE, R0 PULR R7 ENDP ; ------------------------------------------------------------- ; Sets the parallel port data pins to output SetParallelDataOutput PROC PSHR R5 PSHR R0 MVII #ACC_REG_PARALLEL_CONTROL, R0 MVO R0, ACC_REG_INDEX MVI ACC_REG_VALUE, R0 ANDI #$00DF, R0 MVO R0, ACC_REG_VALUE PULR R0 PULR R7 ENDP ; ------------------------------------------------------------- ; Sets the parallel port data pins to input SetParallelDataInput PROC PSHR R5 PSHR R0 MVII #ACC_REG_PARALLEL_CONTROL, R0 MVO R0, ACC_REG_INDEX MVI ACC_REG_VALUE, R0 ANDI #$00DF, R0 XORI #$0020, R0 MVO R0, ACC_REG_VALUE PULR R0 PULR R7 ENDP parallel.pdf 76.49 kB · 1 download Would this make the FujiNet implementation depend on your ACC device? I thought the idea was to define a means to interface the ESP32 directly with the Intellivision, via the cartridge port or something. dZ. Edited December 16, 2022 by DZ-Jay Quote Link to comment Share on other sites More sharing options...
tschak909 Posted December 16, 2022 Author Share Posted December 16, 2022 2 minutes ago, DZ-Jay said: Would this make the FujiNet implementation depend on you ACC device? I thought the idea was to define a means to interface the ESP32 directly with the Intellivision, via the cartridge port or something. dZ. that would be correct, but am trying to learn as much as I can from @JohnPCAE's implementation as I can. The goal for me would be a self contained cartridge. -Thom 1 Quote Link to comment Share on other sites More sharing options...
JohnPCAE Posted December 16, 2022 Share Posted December 16, 2022 (edited) 6 hours ago, tschak909 said: Where does the parallel port sit in the memory map? -Thom All ACC registers are at $007E and $007F. You select the register by writing to $007E and you set (or read) the register's value at $007F. If you've ever done CGA, EGA, or VGA programming, it will look very familiar. I do something similar with my USB card by putting its registers at $007C and $007D (so please don't use those). Edited December 16, 2022 by JohnPCAE Quote Link to comment Share on other sites More sharing options...
tschak909 Posted December 16, 2022 Author Share Posted December 16, 2022 1 minute ago, JohnPCAE said: All ACC registers are at $007E and $007F. You select the register by writing to $007E and you set (or read) the register's value at $007F. If you've ever done CGA, EGA, or VGA programming, it will look very familiar. I do something similar with my USB card by putting its registers at $007C and $007D (so please don't use those). ok was making sure, will have to look at the schematic to see how you've decoded that. -Thom Quote Link to comment Share on other sites More sharing options...
JohnPCAE Posted December 16, 2022 Share Posted December 16, 2022 Just now, tschak909 said: ok was making sure, will have to look at the schematic to see how you've decoded that. -Thom The decoding is done in the Raspberry Pi Pico. It does all of the heavy lifting. It's a dual-core microcontroller. One core talks to the Intellivision bus and emulates a coprocessor and the other core handles video output. Quote Link to comment Share on other sites More sharing options...
JohnPCAE Posted December 17, 2022 Share Posted December 17, 2022 6 hours ago, DZ-Jay said: Would this make the FujiNet implementation depend on your ACC device? I thought the idea was to define a means to interface the ESP32 directly with the Intellivision, via the cartridge port or something. dZ. It does, but right now the ACC is the only thing that provides any sort of external device connectivity to the Inty. As to why I chose a parallel port, it provides a ton of capability while also being an industry standard. You can connect any old printer from the 80's or 90's and it will work as long as you have the software to drive it. Or you could rig a DIN connector to its pins and bit-bang the Commodore 64 IEC protocol if you wanted to. Or you could connect a resistor ladder to the data pins and get crude analog sound. Or anything else you could do with a PC's parallel port. Quote Link to comment Share on other sites More sharing options...
First Spear Posted October 24, 2023 Share Posted October 24, 2023 Is there anything new on this you can share with an untalented spectator on this topic (like me)? Thanks. Quote Link to comment Share on other sites More sharing options...
tschak909 Posted October 24, 2023 Author Share Posted October 24, 2023 1 minute ago, First Spear said: Is there anything new on this you can share with an untalented spectator on this topic (like me)? Thanks. Work on this is dependent on a fully functional parallel bus interface, which the #zx-spectrum team is still working on. Once this is available, we'll be able to move forward on this. If anyone wants to help push it forward in spite of this (e.g. you have an alternative path), please contact us in the discord. https://discord.gg/7MfFTvD -Thom 2 Quote Link to comment Share on other sites More sharing options...
tschak909 Posted May 28 Author Share Posted May 28 Ok, another attempt to push this rock forward... Since some time has passed, I can fill in on some things learned since the last post: We've been able to use the RP2040 microcontroller present in the Raspberry Pico (and similar devices), and most specifically, the PIO macroblock, as a front-end to the ESP32, with it performing any fast reacting bus actions, while connecting to an ESP32 over one of the high speed UARTs (e.g. at approximately 4mb/ps) (1) We have leveraged this, to provide the high speed IWM interactions needed for the Mac68K. (2) We have also used this, (thanks to the work of @jeffpiep) to provide a ROM emulation, and bus I/O decoding for the next iteration of the TRS-80 Color Computer Cartridge. (3) This is being used for the Atari 2600 version of FujiNet to provide the same features as (2), fusing together elements of PlusCart and FujiNet. Point (2) and (3) is what I feel will be most useful for an Intellivision version. This begs the question from those who could answer: FujiNet would be a cartridge device, with a pass-through to plug in another game, which would use the services provided. We could provide a decoded section of memory addresses that attach to the FujiNet, to provide e.g. * A byte for device # * A byte for status * A byte for reading data * A byte for writing data What would be the best way to expose this address space in the memory map so that other games could potentially use the services provided by the FujiNet cart to use the network adapter for networked game use (the network device would be one of many devices exposed by the FujiNet.) If anyone wants to help with starting a bring-up, come join us over in the discord: https://discord.gg/2Ce9guX One of the games that could be quickly ported, could be the 5 Card Stud that we're working across different platforms, e.g. Atari/Apple2: Atari 2600: -Thom 1 Quote Link to comment Share on other sites More sharing options...
+DZ-Jay Posted May 29 Share Posted May 29 Hi, Thom, I joined the Discord channel. I don’t know how much I can contribute to the project, but I am very interested in it. So, if any of my low-level Intellivision-development arcane experience can be of value, I am willing to assist in whichever way I can. dZ. 1 1 Quote Link to comment Share on other sites More sharing options...
tschak909 Posted May 30 Author Share Posted May 30 @DZ-Jay and I had a very productive conversation over the last day and a half! It seems that (and I am stating this here so that I may be potentially corrected): * There is an existing protocol standard in JLP that can be used to be the base-line Fujinet-to-INTV communication protocol. * JLP is implemented in devices like the LTO Flash, but also in the jzIntv emulator. * This means that the FujiNet bring-up could be done using FujiNet-PC, connected to jzIntv. For those working on e.g. jzIntv, and LTO Flash, etc, does this make sense? -Thom Quote Link to comment Share on other sites More sharing options...
+DZ-Jay Posted May 30 Share Posted May 30 3 hours ago, tschak909 said: @DZ-Jay and I had a very productive conversation over the last day and a half! It seems that (and I am stating this here so that I may be potentially corrected): * There is an existing protocol standard in JLP that can be used to be the base-line Fujinet-to-INTV communication protocol. * JLP is implemented in devices like the LTO Flash, but also in the jzIntv emulator. * This means that the FujiNet bring-up could be done using FujiNet-PC, connected to jzIntv. For those working on e.g. jzIntv, and LTO Flash, etc, does this make sense? -Thom By the way, I only mentioned JLP as a model of how your API may be implemented and suggested that since it was fully specified and (I think) open source, you could review how it interacts between the game program and the hardware extensions. I didn’t mean to suggest that JLP out of the box supports a generic API for your purposes. Sorry for the confusion. dZ. Quote Link to comment Share on other sites More sharing options...
tschak909 Posted May 30 Author Share Posted May 30 Just now, DZ-Jay said: By the way, I only mentioned JLP as a model of how your API may be implemented and suggested that since it was fully specified and (I think) open source, you could review how it interacts between the game program and the hardware extensions. I didn’t mean to suggest that JLP out of the box supports a generic API for your purposes. Sorry for the confusion. dZ. Oh I do understand! But I think there may be enough here to build upon, much like we had to do with DriveWire on the TRS-80 CoCo bring-up. Hopefully I can work with the jzIntv maintainer and others to try and establish a solid plan that would be beneficial to all -Thom 1 Quote Link to comment Share on other sites More sharing options...
+DZ-Jay Posted May 30 Share Posted May 30 Sounds great! 👍🏻 dZ. Quote Link to comment Share on other sites More sharing options...
tschak909 Posted June 3 Author Share Posted June 3 OK, trying to figure out where we could place registers for the FujiNet. Any JLP/Intv hardware hackers' input would be most welcome: Let's say we have the following registers: (we can optimize this, but am just providing an example) | Offset | Description |--- |--- | 0 | Device ID (Fujinet Config, Network Device, etc.) | 1 | Status Flags (Ready, Error, etc.) | 2 | Command byte (OPEN, CLOSE, READ, WRITE, STATUS, PARSE JSON, etc.) | 3 | Buffer address HI | 4 | Buffer address LO | 5 | Buffer len HI | 6 | Buffer len LO | 7 | Aux parameter 1 | 8 | Aux Parameter 2 Where could we cram this in the overall memory map? I am reading the JLP documentation, and I see various bits of the memory map marked as "NOT FOR JLP," what does this mean for something like FujiNet? -Thom Quote Link to comment Share on other sites More sharing options...
+DZ-Jay Posted June 3 Share Posted June 3 43 minutes ago, tschak909 said: OK, trying to figure out where we could place registers for the FujiNet. Any JLP/Intv hardware hackers' input would be most welcome: Let's say we have the following registers: (we can optimize this, but am just providing an example) | Offset | Description |--- |--- | 0 | Device ID (Fujinet Config, Network Device, etc.) | 1 | Status Flags (Ready, Error, etc.) | 2 | Command byte (OPEN, CLOSE, READ, WRITE, STATUS, PARSE JSON, etc.) | 3 | Buffer address HI | 4 | Buffer address LO | 5 | Buffer len HI | 6 | Buffer len LO | 7 | Aux parameter 1 | 8 | Aux Parameter 2 Where could we cram this in the overall memory map? I am reading the JLP documentation, and I see various bits of the memory map marked as "NOT FOR JLP," what does this mean for something like FujiNet? -Thom Those are not available. They are reserved for the actual Intellivision hardware -- things like the Intellivoice, ECS, etc. -dZ. Quote Link to comment Share on other sites More sharing options...
tschak909 Posted June 6 Author Share Posted June 6 Would anyone here be interested in helping define the bus protocol that could potentially be used for any system with at least an 8-bit data bus? It would affect not only Intellivision, but potentially every game console that would use a FujiNet. I am genuinely trying to involve others, so that we can get a bus interface that a rough consensus of us would be happy with. -Thom Quote Link to comment Share on other sites More sharing options...
+Lathe26 Posted June 6 Share Posted June 6 3 hours ago, tschak909 said: Would anyone here be interested in helping define the bus protocol that could potentially be used for any system with at least an 8-bit data bus? It would affect not only Intellivision, but potentially every game console that would use a FujiNet. I am genuinely trying to involve others, so that we can get a bus interface that a rough consensus of us would be happy with. -Thom I might be able to help. I've defined other non-retro protocols. However, my bandwidth is limited these days so I can only help somewhat. Quote Link to comment Share on other sites More sharing options...
mr_me Posted June 6 Share Posted June 6 On 6/2/2024 at 8:29 PM, tschak909 said: OK, trying to figure out where we could place registers for the FujiNet. Any JLP/Intv hardware hackers' input would be most welcome: Let's say we have the following registers: (we can optimize this, but am just providing an example) | Offset | Description |--- |--- | 0 | Device ID (Fujinet Config, Network Device, etc.) | 1 | Status Flags (Ready, Error, etc.) | 2 | Command byte (OPEN, CLOSE, READ, WRITE, STATUS, PARSE JSON, etc.) | 3 | Buffer address HI | 4 | Buffer address LO | 5 | Buffer len HI | 6 | Buffer len LO | 7 | Aux parameter 1 | 8 | Aux Parameter 2 Where could we cram this in the overall memory map? I am reading the JLP documentation, and I see various bits of the memory map marked as "NOT FOR JLP," what does this mean for something like FujiNet? -Thom Here's the Intellivision memory map. http://spatula-city.org/~im14u2c/intv/jzintv-1.0-beta3/doc/programming/memory_map.txt The Intellicart used some of those addresses marked reserved, although write only. Would this be a device that passes through the cartridge port for other cartridges? 1 Quote Link to comment Share on other sites More sharing options...
+DZ-Jay Posted June 6 Share Posted June 6 23 minutes ago, mr_me said: Would this be a device that passes through the cartridge port for other cartridges? I think that is the case, which presents a problem in laying out the memory space without colliding with the JLP and other similar extensions. That is why I suggested he take a look at what JLP does and how it works, to see how best to accommodate his requirements alongside it. dZ. 1 Quote Link to comment Share on other sites More sharing options...
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