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F18A VDP (VGA version) Interest Check


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I have found a supplier that can provide the required Xilinx IC to manufacture the original F18A (VGA Connector).  I have ordered a handful of chips to verify, and they are good.  These chips have skyrocketed in price over the last couple of years.  If you are interested in purchasing a VGA version of the F18A, please go to my link at the bottom of this post to submit an interest.  With the price of the chips be aware that the price of the unit will be between $150 - $175 USD.  This is dependent on how many I order at one time.


Interest form:  https://forms.gle/2MQAH79SUqqCuQGz5


The F18A has been installed in the following systems:

TI-99/4A Home Computer
ColecoVison Game Console (1)
ColecoVision ADAM Computer (1)
Toshiba HX-10 MSX1 Computer
Toshiba Pasopia-IQ MSX1 Computer
JVC Victor HC-7 MSX1 Computer
Yamaha CX5M MSX1 Computer
SpectraVideo 328 Computer (1)
Tomy Tutor (1)
SEGA SG-1000 (2)
SEGA SC-1000II (replaced a TMS9118 VDP)
Telegames Personal Arcade
Powertran Cortex
Memotech 500 and 512 (2)


Features with latest firmware (1.9):


  • 80-column (T80) mode.
  • Position-based attributes for T80 mode, so each tile can have its own foreground and background color.
  • 64 programmable 12-bit (4096) color palette registers.
  • High-speed “data port mode” for fast palette register updating.
  • Three enhanced color modes (ECM) that provide 1, 2, or 3 bits-per-pixel allowing 2, 4, or 8 colors per-pixel for each tile and sprite.
  • 32-sprites on a line at once (can eliminate sprite flicker if software did not implement sprite-rotation).
  • Each sprite can have its own size (8x8 or 16x16), and X/Y pattern flip.
  • 30-column mode that provides 32x30 tiles (same as the NES).
  • Two independent tile-layers, each with their own name, color, and pattern table base addresses.
  • Per-tile attributes so each tile can have its own foreground and background color, priority over sprites, X/Y pattern flip, and transparency.
  • Independent horizontal and vertical pixel-scrolling for each tile layer.
  • Tile page sizes of 1x1, 2x1, 1x2, and 2x2 to support edge-to-edge pixel scrolling.
  • Bitmap layer with programmable size from 1x1 to 256x192 pixels, pixel locatable, 4-colors per pixel, 16-colors per pixel “fat pixel” mode, sprite priority, and palette select.
  • Programmable horizontal-line interrupt.
  • Programmable signed increment value for the VDP Address Register.
  • Ability to read all VDP Registers.
  • Programmable 46-bit decimal counter with 10ns (nanosecond) precision (can count 18.2044 hours with 10ns accuracy).
  • A 100MHz TMS9900-based “GPU” processor that can execute programs in VRAM, has full access to all VDP Registers, a high-speed DMA, and dedicated pixel-plotting and address instructions.
  • Virtual scan-lines for a retro CRT look.
  • VGA 640x480 60Hz video output.


If you are interested in

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