Thinking of getting a new Atari 800XL board made....

[+scorpio_ny]

Thank you very much for the clarification! I happy to see new designs that gives one the ability to be less dependent on legacy components.

[Overange]

2 hours ago, reifsnyderb said:

Since I just posted this elsewhere, here's the schematic for the banking logic:

 

 

 

I'll need to use one of the pins (i.e. 13) for a /halt latch and still have 2 other macro cells available in the event I need extra logic.

 

In the schematic above, PB2-PB5 are from the PIA chip.  SRA14-SRA16 go to pins A14-A16 on the SRAM chip.

 

For normal operation, if PB4 and PB5 are high, SRA16 will be set low, SRA14 will be equal to AR14, and SRA15 will be equal to A15.

 

With CPU banking, PB4 will be set low, /halt will have to be high, SRA16 will be set high, SRA14 will be equal to PB2, and SRA15 will be equal to PB3.

 

With ANTIC banking, the /halt latch will be checked to see if /halt is called.  If PB5 is set low and /halt is called, SRA16 will be set high, SR15 will be equal to PB2, and SRA15 will be equal to PB3.

 

The /halt latch, on Pin 13, can be configured such that .d is from pin 9 and it is triggered by sending a pulse out pin 16 when Phi2 drops.  The capacitor, C75, will ensure a slight delay on the clock pulse.  The value of this capacitor will have to be determined through experimentation.  However, it shouldn't take much.  I've used a 4.7nF capacitor for a Read/Write Late delay on an 800 board.  Something similar should work fine.  I'll have to fine tune it with the scope.

 

I also positioned the inputs and output so that if the ATF16V8B is omitted, A14 is across from SRA14, A15 is across from SRA15, and ground is across from SRA16.  This will allow for easy jumpering without the chip.   🙂

 

 

 

 

 

Not trying to over complicate things  

 

When I created my prototype board to test the performance of the AS6C1008-55PCN, I made a silly mistake that oddly works...

 

I accidentally fitted an AS6C4008-55PCN, and it works perfectly.

 

The main differences are in the pinout assignments; the AS6C1008 uses pin 30 as CE2, and the AS6C4008 uses this as A17, with Pin 1 being A18.

This is my 64k Base memory Schematic from my 800xl remake, and CS2 Pin30 is the Buffered o2.

 

I don't want to explode my mind trying to figure out why it worked, but hey...

 

However, could you make it selectable in the design between the lower-cost memory option, the 1008 version, and, with some simple changes, the ability to fit a 4008 and utilize the extra available memory?

 

This way, you can have different memory options available.

 

Is this something that could be achieved?

[reifsnyderb]

2 hours ago, Overange said:

Not trying to over complicate things  

 

When I created my prototype board to test the performance of the AS6C1008-55PCN, I made a silly mistake that oddly works...

 

I accidentally fitted an AS6C4008-55PCN, and it works perfectly.

 

The main differences are in the pinout assignments; the AS6C1008 uses pin 30 as CE2, and the AS6C4008 uses this as A17, with Pin 1 being A18.

This is my 64k Base memory Schematic from my 800xl remake, and CS2 Pin30 is the Buffered o2.

 

I don't want to explode my mind trying to figure out why it worked, but hey...

 

However, could you make it selectable in the design between the lower-cost memory option, the 1008 version, and, with some simple changes, the ability to fit a 4008 and utilize the extra available memory?

 

This way, you can have different memory options available.

 

Is this something that could be achieved?

An AS6C4008 would work fine in place of an AS6C1008 as long as pin 1 was grounded or set to +5VDC.  If pin 1, on an AS6C4008, were to drift due to not being connected the system would crash.

 

For your purpose, you can eliminate U28C and tie /OE to ground.  (Check the truth table in the datasheet, /OE really isn't needed and can be tied to ground.  CS2 could be tied to +5VDC as well.)

 

With an AS6C4008, it wouldn't take much to use PORTB Pin 5 to gain access to 128k of extended memory.  PORTB Pin 6 would have be extended to turn that into 256k of extended memory or 320k of total memory.

 

This is, of course, possible.  (It's also called feature creep.)

 

Edit to add:  It wasn't easy extending PORTB 2-5 over to the SRAM area.  That 6th line will be even worse.  😞

 

Edit again:  Ok.....6th line can be extended.  I'll add it.   😕

 

 

Edited November 9, 2023 by reifsnyderb

[reifsnyderb]

I am left wondering if the AS6C1008 and AS6C4008 aren't the exact same chips, internally, and the company just connects them differently them sells them at different prices.

[reifsnyderb]

Ok.  It should now be possible to program the chip to use the AS6C4008 for 320k.  I only have 2 macro cells available for using a AS6C1008 for 128k w/XE banking, however.  I'll have to do the WinCupl code prior to ordering the board to make sure everything will work as planned.  Though, it may be possible to just install the ATF16V8B PLC in an extra socket that is on top of the existing socket to use an AS6C1008 instead of an AS6C4008 and leave some pins unconnected.

[+mytek]

2 hours ago, reifsnyderb said:

CS2 could be tied to +5VDC as well.

I wouldn't advise doing that. Writes to memory or I/O shouldn't be done unless Phi2 is HIGH, in order to have reliable data transfer.

 

Reference: 'Qualifying' write operations

 

Normally it's done like this...

But where there are additional CS inputs on the memory device, those work fine as well, thus eliminating the need for external logic.

[reifsnyderb]

17 minutes ago, mytek said:

I wouldn't advise doing that. Writes to memory or I/O shouldn't be done unless Phi2 is HIGH, in order to have reliable data transfer.

 

Reference: 'Qualifying' write operations

 

Normally it's done like this...

But where there are additional CS inputs on the memory device, those work fine as well, thus eliminating the need for external logic.

Never mind.  I just realized you are referring to his logic for SRAM access.  Yeah, you are correct.

Edited November 10, 2023 by reifsnyderb

[+mytek]

21 minutes ago, reifsnyderb said:

Never mind.  I just realized you are referring to his logic for SRAM access.  Yeah, you are correct.

There are at least a dozen different ways to accomplish it, but it's imperative that writes to memory don't happen unless Phi2 is HIGH.

 

On the 576NUC+ the extra Chip Enable lines on the SRAM kept the external logic simple.

 

But there were no PBI concerns on that system.

 

Where that does matter, the PBI /EXTSEL line needs to be factored in as well, as can be seen in the 1088XEL circuit below.

 

[reifsnyderb]

1 hour ago, mytek said:

There are at least a dozen different ways to accomplish it, but it's imperative that writes to memory don't happen unless Phi2 is HIGH.

 

You just got me checking as to how I have it setup on the new board.  I tied CE to +5VDC, /CE to a ATF16V8B, and /WriteEnable to the same ATF16V8B.  In the ATF16V8B, /CE and /WE are only active when Phi2 is high.

[reifsnyderb]

Here's the code for the ATF16V8B that replaces the 74LS138 and other memory control chips.

 

The IO signal comes from the MMU and goes low when an address from $D000-$D7FF is called.

Other signals should be adequately described, below.

 

The !WRT signal replaces the latched write signal set by the 74LS375 on a normal 800XL.

 

 

 

Name       800XL 2023 Advanced PCB Remake;
Partno     NA;
Date       11/02/2023;
Revision   00;
Designer   Brian Reifsnyder;
Company    N/A;
Assembly   2023 Advanced PCB Remake - For the Atari 800XL;
Location   U2;
Device     g16v8as;

/******************************************************************/
/*    800XL 2023 Advanced PCB Remake                    */
/*                                                                */
/*                                                                */
/******************************************************************/
/*  Allowable Target Device Types: ATF16V8                        */
/******************************************************************/

/**  Inputs  **/
Pin  01    = A8                    ;  /* A8                    */
Pin  02    = A9                    ;  /* A9                    */
Pin  03    = A10                  ;  /* A10                    */

Pin 04    = PBI_RAM_En   ;  /* PBI RAM Enable    */

Pin  06    = Phi2S               ;  /* Phi2 Sally                */
Pin  07    = MMU_CI          ;  /* !MMU CAS Inhibit            */
Pin  08    = RW                   ;  /* RW From Sally                */
Pin  09    = PB_EXTSEL    ;  /* !EXTSEL                    */
Pin  11    = IO                     ;  /* !IO                    */

/**  Outputs  **/
Pin  12    = WRT              ;  /* !Write (Synchronized w/Phi2 Sally)    */
Pin  13    = SRAM_CE    ;  /* !SRAM CE                */
Pin  16    = D5xx              ;  /* !Cartridge Control            */
Pin  17    = D3xx              ;  /* !PIA CE                    */
Pin  18    = D2xx              ;  /* !POKEY CE                */
Pin  19    = D0xx              ;  /* !GTIA CE                */

/**  Logic Equations  **/
/**  # is or **/
/**  ! is not **/

!WRT               =    !RW & Phi2S;

!SRAM_CE      =    MMU_CI &  PB_EXTSEL & Phi2S #

                             !IO & A10 & A9 & PB_EXTSEL & Phi2S & PBI_RAM_En;    /* PBI RAM at D6xx to D7FF */

!D5xx              =    !IO & A10 & !A9 & A8;

!D3xx              =    !IO & !A10 & A9 & A8;

!D2xx              =    !IO & !A10 & A9 & !A8;

!D0xx              =    !IO  & !A10 & !A9 & !A8;

 

 

 

Edit:  Changed PBI RAM enable logic.

 

Edited November 10, 2023 by reifsnyderb

[Overange]

2 hours ago, reifsnyderb said:

Here's the code for the ATF16V8B that replaces the 74LS138 and other memory control chips.

 

The IO signal comes from the MMU and goes low when an address from $D000-$D7FF is called.

Other signals should be adequately described, below.

 

The !WRT signal replaces the latched write signal set by the 74LS375 on a normal 800XL.

 

 

 

Edit:  Changed PBI RAM enable logic.

 

So does these mean you now have the following options

 

Option 1 =  1008 SRAM fitted

 

Mode 1 = 64K Base

Mode 2 = 64K base and 128K Extended

 

Option 2 = 4008 SRAM fitted

 

Mode 1 = 64K Base

Mode 2 = 64K Base and 320K Extended

 

So therefore if I wanted to fit a U1MB, I would set the board to 64K mode and the U1MB would work as expected?

 

At least by having 2 SRAM Device Options, gives you more flexibility and choice  

 

6 hours ago, mytek said:

 

Where that does matter, the PBI /EXTSEL line needs to be factored in as well, as can be seen in the 1088XEL circuit below.

 

 

That's the design I went with  

 

 

[reifsnyderb]

14 minutes ago, Overange said:

So does these mean you now have the following options

 

Option 1 =  1008 SRAM fitted

 

Mode 1 = 64K Base

Mode 2 = 64K base and 128K Extended

 

Option 2 = 4008 SRAM fitted

 

Mode 1 = 64K Base

Mode 2 = 64K Base and 320K Extended

 

So therefore if I wanted to fit a U1MB, I would set the board to 64K mode and the U1MB would work as expected?

 

At least by having 2 SRAM Device Options, gives you more flexibility and choice  

 

Those are some of the options.  In theory, this is the reasonable option list:

 

Option 1:  AS6C1008 by itself.  4 jumpers installed at U26 -- 64k base only

Option 2:  AS6C1008, ATF16V8B installed at U26 and programmed for RAMBO extended RAM -- 64k base and 64k extended

Option 3:  AS6C1008, ATF16V8B installed at U26 and programmed for XE banking, timing capacitor installed -- 64k base and 64k CPU or XE banked.

Option 4:  AS6C4008, ATF16V8B installed at U26 and programmed for RAMBO banking -- 64k base and 256k extended.

 

Of course, technically, there are other options like AS6C4008 by itself, some jumpers installed -- 64k base only.  But that would be ridiculous.  🙂

 

 

 

 

 

 

Edited November 10, 2023 by reifsnyderb

[Overange]

6 minutes ago, reifsnyderb said:

Those are some of the options.  In theory, this is the reasonable option list:

 

Option 1:  AS6C1008 by itself.  4 jumpers installed at U26 -- 64k base only

Option 2:  AS6C1008, ATF16V8B installed at U26 and programmed for RAMBO extended RAM -- 64k base and 64k extended

Option 3:  AS6C1008, ATF16V8B installed at U26 and programmed for XE banking, timing capacitor installed -- 64k base and 64k CPU or XE banked.

Option 4:  AS6C4008, ATF16V8B installed at U26 and programmed for RAMBO banking -- 64k base and 256k extended.

 

Of course, technically, there are other options like AS6C4008 by itself, some jumpers installed -- 64k base only.  But that would be ridiculous.  🙂

 

 

 

 

 

 

I think it is a very good set of options

 

Or Option 1 leave U26 Empty and have 4 headers nearby to set 64K Base only??

 

And the other 3 options would mean 3 different JED Files for each option??

 

And would Option 3 technically mean your 800XL would become an 130XE?

 

Sorry for the questions, its been a long night, need sleep 😴

Either way, this is some cool options.

 

I may have to borrow it cough cough  

 

[reifsnyderb]

6 hours ago, Overange said:

Or Option 1 leave U26 Empty and have 4 headers nearby to set 64K Base only??

 

I just have the pins marked so jumpers can be installed.  If the jumpers are installed, only U9 and C34 are needed.

 

 

• Edit

 

 

6 hours ago, Overange said:

And the other 3 options would mean 3 different JED Files for each option??

Yes.  Install a socket for U26 and program the chip for the memory option.

 

6 hours ago, Overange said:

And would Option 3 technically mean your 800XL would become an 130XE?

Yes.  A very, very, nice 130XE in an 800XL case with a much better keyboard, cartridge slot at a better location, a switch in the back to select the OS/BASIC combo (re-purposed channel select switch), and a proper PBI.     🙂

 

 

6 hours ago, Overange said:

I may have to borrow it cough cough  

 

 

Feel free.  🙂

 

 

 

Edited November 10, 2023 by reifsnyderb

[reifsnyderb]

Ok.  I've got composite video working.  The 1k resistor, that we added to the color circuit, needs jumped to ground to get proper color with composite video.  I checked composite with the 800 and it's similar.  It's not great.  But it's similar.  Maybe it would look better on a smaller TV.  If it wasn't for the graphics artifacts, I don't know why anyone would want to use composite video anyhow.

 

Edit to add:

 

Here's the video circuit in it's entirety:

 

 

For composite video:  Install R57, C54, and R67.  Remove R65 and install jumper to ground.

 

For S-Video:  R57, C54, and R67 are optional.  (Video looks better without them.)  Install R65.

 

 

 

 

 

Edited November 10, 2023 by reifsnyderb

[Overange]

39 minutes ago, reifsnyderb said:

Ok.  I've got composite video working.  The 1k resistor, that we added to the color circuit, needs jumped to ground to get proper color with composite video.  I checked composite with the 800 and it's similar.  It's not great.  But it's similar.  Maybe it would look better on a smaller TV. 

If it wasn't for the graphics artifacts, I don't know why anyone would want to use composite video anyhow.

 

Edit to add:

 

Here's the video circuit in it's entirety:

 

 

For composite video:  Install R57, C54, and R67.  Remove R65 and install jumper to ground.

 

For S-Video:  R57, C54, and R67 are optional.  (Video looks better without them.)  Install R65.

 

 

 

 

 

Or you could...

 

Add jumper headers at 1 and 2 to relink those paths.

Then another at 3 to short R65.

 

This way you can keep the components but have the option for Composite with all three links installed??

 

 

Its handy to have composite for those mini monitors that have composite input only.

 

I have a couple that i use for bench testing old systems.

 

 

Edited November 10, 2023 by Overange

[reifsnyderb]

I added a couple of jumpers to enable composite video.  Here's the latest board rendering.  I need to do some more silk screen work, yet.  But I think this is pretty close to what I'll be ordering.

 

[reifsnyderb]

On 10/24/2023 at 7:37 PM, kheller2 said:

128K XE Antic/CPU mode please.

 

I need to write the WinCupl code to verify everything will fit.  In theory, it should now be added.

[reifsnyderb]

I wanted to make sure the code with fit the ATF16V8 (in registered mode) to do 130XE style banking with an AS6C1008.  Here is the pseudo code:

 

SRA17 = !Pin5;                                                           /* Pin 5 always low, so set CE2 high.  */

SRA14 = A14 & !A15 & PB4 & PB5 #                         /* = A14 in banked region and banking off */
               A14 & A15 #                                                 /* = A14 in non-banked high regions */
               A14 & !A15 & PB4 & PB5 #                          /* = A14 when banking is off and bank region */
               PB2 & A14 & !A15 & !PB4 #                         /* = PB2 when CPU banking and bank region */
               PB2 & A14 & !A15 & !PB5 & !HALTL;           /* = PB2 when ANTIC banking, bank region, and !halt */

SRA15 = A14 & A15 #                                                 /* = A15 in non-banked high regions */
               !A14 & A15 #                                                /* = A15 in non-banked high regions */
                PB3 & A14 & !A15 & !PB4 #                        /* = PB3 when CPU banking and bank region */
                PB3 & A14 & !A15 & !PB5 & !HALTL;         /* = PB3 when ANTIC banking, bank region, and !halt */

SRA16 = A14 & !A15 & !PB4 #                                   /* Use banked RAM when bank region and CPU banking */
                A14 & !A15 & !PB5 & !HALTL;                    /* Use banked RAM when bank region, ANTIC banking, and !halt */

CLOCKP = !Phi2;                                                        /* Clock pulse to set HALTL latch (will have delay with timing cap) */

HALTL = !HALT;                                                           /* Use SRA18 for HALTL as pin is NC for AS6C1008 */

 

 

To do this with an AS6C4008 would require that an ATF22V10 be used as I am taking advantage of the fact that pin 1 on an AS6C1008 is NC and using the connection to that pin as a halt latch.  On the AS6C1008, pin 30 is CE, so I need to use that particular output, from the ATF16V8, to hold CE to high.

 

 

 

 

 

Edited November 11, 2023 by reifsnyderb

[Jfcatari]

Looking even better now with the latest revision!

Where's my donor 600XL when I need it. 

 

Bradley at Best Electronics has socketed 600XL mobos up for sale for $99!

Edited November 11, 2023 by Jfcatari

[bfollowell]

23 minutes ago, Jfcatari said:

Looking even better now with the latest revision!

Where's my donor 600XL when I need it. 

 

Bradley at Best Electronics has socketed 600XL mobos up for sale for $99!

 

He actually doesn't have those any longer. Those are listed as sold out on his addendum page. He does show 800XL motherboards though.

 

Atari 800XL NTSC U.S. Mother Board Populated  CA061854  $129.95

 

https://www.best-electronics-ca.com/addendum.htm

 

 

Edited November 11, 2023 by bfollowell

[+scorpio_ny]

I going am to try to build one with as little Atari custom chips as possible. All we need now is a modern replacement for the Antic chip.

 

[reifsnyderb]

More work done on the board.  Lots of little tweaks.  For example, the transistor footprint in the audio circuit was a very tight and easy to bridge when I soldered it in.  This board uses an alternate footprint so as to make it a little easier.  I also found out the breadboard holes were a little tight when I used one.  Removing the solder from the hole was difficult and I botched up the solder mask due to the copper layer being close by.  So, both breadboard areas no longer have any copper infringing upon them and the holes have been expanded to 1mm.  I think all of the silkscreen labeling is finished.  I want to change the fuse footprint around a little as the holes are tiny.  (The fuse is optional and I haven't experimented with it yet.  A 2 AMP fuse would be preferable.)  I also noticed that the rectangular holes for the cartridge plastic thingy need to be checked as one was a little loose.  I'll check them against a factory board with a dial caliper and adjust if necessary.

 

Also, the new boards have a hold-down resistor so the ROM bank select switch is optional.  Or, if the old switch fails, bank 0 will still work.

 

 

 

Edited November 11, 2023 by reifsnyderb

[reifsnyderb]

12 minutes ago, scorpio_ny said:

I going am to try to build one with as little Atari custom chips as possible. All we need now is a modern replacement for the Antic chip.

 

I am going to use this prototype board and experiment with a W65C02 soon.  I am very interested in seeing if it will work with nothing more than a PLC.   🙂

 

[reifsnyderb]

I think the board is finalized.

 

Added are two more breadboard areas.  The top left region has a +5VDC rail and a GND rail.  There are no other interconnects in this area as it's somewhat narrow.  The other two breadboard areas have +5VDC rails and GND rails.  In addition, they also have interconnects like a conventional breadboard so as to make adding other connections easier.

 

Also, there are 2 fuse options.  I used the unused area to the left of the monitor jack for a 5x20 fuse.  This board can also be very basic with just 64k or have an EMMU installed to turn it into a 130XE type system, a 128k RAMBO system, or a 320k RAMBO system.