Self Learning Kicad as I design a FDC/IO card

[RickyDean]

Well last night I started taking the plunge into trying to design a FDC/IO card, in Kicad, on the order of a Corcomp FDC to begin with, but transitioning over to the SMC super IO chips I have. Just getting the outline was a feat for me, I could've done this with Autocad in an hour or less, but this took me till 2am last night and an 1 hour this morning, to figure out the details of the outline. Still some tweaking to do before adding via's, traces, and so forth. This won't be a copy of an CC card as I'm going to add buffers and rearrange the footprints, maybe adding the ability to use both 1773 or 2793 chips or similar. I'm going to have shoulder surgery in the next two weeks, due to a work related incident that tore a tendon loose and 3 more barely holding on on my right shoulder. Workers Comp is trying to say it didn't happen, but I'll be fighting it. But I'll need to do something while I'm recuperating, so I thought this may be a good time to teach myself something useful. 

 

[GDMike]

2 hours ago, RickyDean said:

Well last night I started taking the plunge into trying to design a FDC/IO card, in Kicad, on the order of a Corcomp FDC to begin with, but transitioning over to the SMC super IO chips I have. Just getting the outline was a feat for me, I could've done this with Autocad in an hour or less, but this took me till 2am last night and an 1 hour this morning, to figure out the details of the outline. Still some tweaking to do before adding via's, traces, and so forth. This won't be a copy of an CC card as I'm going to add buffers and rearrange the footprints, maybe adding the ability to use both 1773 or 2793 chips or similar. I'm going to have shoulder surgery in the next two weeks, due to a work related incident that tore a tendon loose and 3 more barely holding on on my right shoulder. Workers Comp is trying to say it didn't happen, but I'll be fighting it. But I'll need to do something while I'm recuperating, so I thought this may be a good time to teach myself something useful. 

 

So sorry about that arm of yours. Get well soon.

The software will probably get easier the more you use it in the more tricks you find out, it's probably like everything else it's just going to take time.

[+FarmerPotato]

Frustrating in KiCad: Poly lines for the edge cuts (or anything). I try to put the top left at round numbers, if not 0,0. On each segment, I edit properties to make sure they are straight. You can also do this with a text editor on the .sch file!

 

Save your edge outline in a file by itself! Or convert it to a Footprint (I forget how I did that, maybe copy-paste?)

[RickyDean]

10 minutes ago, FarmerPotato said:

Frustrating in KiCad: Poly lines for the edge cuts (or anything). I try to put the top left at round numbers, if not 0,0. On each segment, I edit properties to make sure they are straight. You can also do this with a text editor on the .sch file!

 

Save your edge outline in a file by itself! Or convert it to a Footprint (I forget how I did that, maybe copy-paste?)

Yes, it was a job getting this outline dealt with, but this should do the trick, maybe some small changes here and there. Got most of the IC's represented in the schematic, except the MM2114N sram and the two PAL12V6 chips, may have to go ahead with GAL16V8 chips instead.

[+FarmerPotato]

Re: GAL16V8: (some of?)  these are reprogrammable, unlike PAL.  The chip still in mass production is the ATF22V10C starting in  DIP24 (I use the PLCC).  TL-866 does them. One of those might absorb the two 12V6. 

(22V10 has 10 I/O and 12 input only. So can't do  12 outputs.)
 

 

 

 

[RickyDean]

2 hours ago, FarmerPotato said:

Re: GAL16V8: (some of?)  these are reprogrammable, unlike PAL.  The chip still in mass production is the ATF22V10C starting in  DIP24 (I use the PLCC).  TL-866 does them. One of those might absorb the two 12V6. 

(22V10 has 10 I/O and 12 input only. So can't do  12 outputs.)
 

 

 

 

Understood, I just don't have enough knowledge yet, to make that happen, but it might be something that I'll pick up on. Right now between other things going on, I'm just trying to get the basics down on creating this board. The idea at this point is to recreate the CC FDC board, but with a twist, having locations to put a WD1773 or a WD2793, so if one becomes hard to find for replacement, the other can be substituted without a daughter board. Then if this works, I will then plan out and try to  build a board with a multi IO footprint, to use the SMC FDC37C5665 and try to get as much of the functions working as I'm able. I'm not retired yet, though this shoulder damage I suffered recently at work may change my mind. My old mind has to absorb new input and try to put that into use. But don't stop giving input, I appreciate the knowledge here on this forum and will try to use what information I get, here in this, and other endeavors. 

[+FarmerPotato]

OK, probably better to stick with two PAL chips. If they are far apart. 
 

But do get an EEPROM/EEPLD eraseable! For instance PALCE16V8 is still made and cheap. Or ATF16V8C is current. 
 

[RickyDean]

3 minutes ago, FarmerPotato said:

OK, probably better to stick with two PAL chips. If they are far apart. 
 

But do get an EEPROM/EEPLD eraseable! For instance PALCE16V8 is still made and cheap. Or ATF16V8C is current. 
 

Yes, that is part of the plan to use Gal's or the ATF's to replace the Pal' and not worry about locking them. I did find a site that made model set of the MM2114N sram, https://componentsearchengine.com/part-view/MM2114N/Texas Instruments. So now I have this, I can add to the schematic without making my own.

[+FarmerPotato]

The 2114 1Kx4 will be upwardly compatible with any static RAM. For instance the super-common 6264. Just ground the unwanted address pins. It's just as period correct too!

[matthew180]

I'm a big fan of KiCAD, been using it since 2015 when CERN started making contributions, and I have used it for all the F18A revisions, and all other PCB projects.

 

Take your time, ask questions, learn the quirks (as all software has them).  A few pointers:

 

* Always use the imperial 0.1" (or 2.54mm) grid for schematics, or some exact half (0.05" / 1.27mm) or multiple.  Always make symbols on this grid as well.  This is a quirk from the older years that is still with us, and you will be very sad if you do not stick to that grid in the schematics.  The wires and node connections need to be on that grid.

 

* Grids do not matter in the PCB editor, but I recommend metric (about 0.1mm) since most parts are metric these days.  However, if you plan to stick will all legacy through hole, then an imperial grid will probably work out.

 

* Start with the schematic and always import changes into the PCB.  That is the intended workflow and will make things much easier.

 

* Please please please use wires instead of net-labels for connecting things (but do label all net wires!), after all, that's what a schematic is for (showing connections graphically).  Try to have inputs on the left of a sheet, outputs on the right.  A schematic should be clear and logical, have a signal flow from left-to-right, top-to-bottom, and contain all the information you need to do layout, troubleshooting, and write software for the design. Include notes, include photos of connectors, etc..  Take a look at some older coin-op schematics for examples.  There seems to be a "new" way of doing schematics where everything is just net-labels and random placement of components, etc. being adopted all over the place, and it is a nightmare for people other than the ones making the design (and will even suck for the designer 6 months to a year from now).

 

* Use more than 1 sheet (hierarchical schematic), group components by function, use hierarchical labels to connect off-sheet nets.  It is not that hard.  The first sheet becomes a block diagram, i.e. a sheet with boxes and top-level connections that contain the other sheets.  Just select "draw hierarchical sheet", draw the box, double-click the enter the sheet.  KiCAD is getting better with this too, and I think 8.x will have some changes for working with sheets.  Keep the "Schematic Hierarchy" view open for quick navigation.

 

Edited December 25, 2023 by matthew180

[Tursi]

8 hours ago, matthew180 said:

There seems to be a "new" way of doing schematics where everything is just net-labels and random placement of components, etc. being adopted all over the place, and it is a nightmare for people other than the ones making the design (and will even suck for the designer 6 months to a year from now).

I ran into this last week for the first time... Very confusing and took me a while to figure out what they were doing.

 

[Shift838]

Like all new applications take your time to learn it.  I have started learning Kicad myself to be better versed.  I am pretty fluent in Eagle as that is what I have designed most of my boards in.

 

I did design one so far in Kicad, a small one just to get my feet wet and start learning it.  

[matthew180]

On 12/26/2023 at 2:28 AM, Tursi said:

I ran into this last week for the first time... Very confusing and took me a while to figure out what they were doing.

 

 

At work we hired a firm to do some design work, and even they tried to give us designs in that style.  We had them rework the schematics with lines, pull-ups oriented "up", ground oriented "down", things spaced out, centered on the pages, etc..  I don't know WTF is happening in the engineering disciplines these days, but from what I have been seeing, it sucks.  It is like the wild-west of software development is leaking over into more traditional areas of science and engineering and causing erosion.

 

23 hours ago, Shift838 said:

I did design one so far in Kicad, a small one just to get my feet wet and start learning it. 

 

Even though this is slightly off topic (although we are making TI-related  designs), I'm happy to discuss / share anything KiCAD.  The KiCAD forum is also active, and there is a KiCAD Discord channel as well.

 

[Artoj]

3 hours ago, matthew180 said:

It is like the wild-west of software development is leaking over into more traditional areas of science and engineering and causing erosion.

Just a note, in the 1960's ( I was a young lad LOL) I looked and studied old radio/TV valve schematics and they made a lot of sense, I used that way of doing things by hand until computer CAD came along, it can make you lazy, so you must stick to what works, not just for yourself but others who will venture into your "schemes" and try to decipher them. Just like when notating assembly, or complex algorithms in other languages, spend the extra time to explain your choices. I try to avoid nets, but you have no choice at times, when you have too many cross connections. Great topic, I am still testing out KICAD, regards Arto.  

[+FALCOR4]

17 hours ago, matthew180 said:

At work we hired a firm to do some design work, and even they tried to give us designs in that style.  We had them rework the schematics with lines, pull-ups oriented "up", ground oriented "down", things spaced out, centered on the pages, etc..  I don't know WTF is happening in the engineering disciplines these days, but from what I have been seeing, it sucks.  It is like the wild-west of software development is leaking over into more traditional areas of science and engineering and causing erosion.

There's a lot of truth in that.  When I started, we had an incredible engineering guide book that was an absolute treasure.  It covered wiring, connectors, schematic generation, component selection, environmental considerations, etc.  Sometime afterwards, it disappeared when the organization "re-organized."  If you weren't one of the lucky ones who kept a copy, it was lost to eternity.  Unfortunately, those were the days of the typewriter so there is no online copy, at least not that I've found that has been uploaded.  Over the years that followed I could see the new engineers coming in repeating mistakes and relearning the hard way because they didn't have the benefit of a mentor or proper guidance.  I called it the "divide by zero" problem, when will we ever learn? 🙂

[+dhe]

@RickyDean any files you can share with us?

[RickyDean]

4 hours ago, dhe said:

@RickyDean any files you can share with us?

No, not really yet, tinkered some with the Kicad the other night as seen in the picture. Been working on other projects. 

[RickyDean]

Here is a slightly updated view, I haven't been able to spend a lot of time on this as I've been dealing with medical, lawyers, building pico's and other side car expansion as well as trouble shooting . I know Excuses....Excuses.

 

Edited March 4 by RickyDean
added new picture

[matthew180]

15 hours ago, RickyDean said:

I know Excuses....Excuses.

 

This is a hobby, you don't need to make excuse (and certainly not to anyone here).

 

Any reason you don't have all the chips in a horizontal orientation?  The buffers at the bottom are functional in that orientation, since I believe the input and output pins are on opposite sides of the chips.  Since the internal signals interface with the other chips on the board, keeping the same orientation might make routing easier.

 

I am also a fan of functionality first, so chip orientation is secondary to cleaner routing.  But, if cases like this where it is all mostly lower speed, and you have very large boards, you could probably do any orientation you want without much trouble.

 

Also, be careful of chips too close to the edge, there may be mechanical keep-out areas.  Always think about the assembly process, and give yourself room to work.  Things always look further apart in the software layout then they are in reality.  Use the 3D viewer to check clearances.

 

Update to KiCAD 8 (if you have not already).

[RickyDean]

Here's a 3d view of what I've got so far. This is Kicad 8

[+Ksarul]

Just a random thought, here. The second row of chips from the top might work a bit better if they move down just a bit to align with the single large chip to the left of them. That widens the track raceway between the first and second row of chips and it optimized the space below both of those larger chips to maximize available space for traces. Routing can always be a pain, so having lots of useful space to work with is sometimes very beneficial.

[RickyDean]

I decided first to get the traces set up as a CC2793, so here is a view of that. I took scanned photo's that I had of the Corcomp FDC and converted them to BMP photos then placed that into the pcb as a background image then ran traces and via's according to what was seen. The photos were slightly skewed and would not align right with my work, but I ran them best I could to come close to the photos. This is the result and even it is not quite finished, but I'm getting there. Making it pretty will come soonafter I get the components in and ground and voltage planes in. Then when I have a completed version of the CC 2793 board then I will continue to move IC's around and add the other WD1773 ic footpint.

Edited March 22 by RickyDean
spelling, added content

[Gary from OPA]

9 minutes ago, RickyDean said:

I decided first to get the traces set up as a CC2793, so here is a view of that. I took scanned photo's that I had of the Corcomp FDC and converted them to BMP photos then placed that into the pcb as a background image then ran traces and via's according to what was seen. The photos were slightly skewed and would not align right with my work, but I ran them best I could to come close to the photos. This is the result and even it is not quite finished, but I'm getting there. Making it pretty will come soonafter I get the components in and ground and voltage planes in. Then when I have a completed version of the CC 2793 board then I will continue to move IC's around and add the other WD1773 ic footpint.

Just remember there is two types of PEB, one that has the card slot metal all the way up to the top, as such make sure there enough spacing for the right for the internal FDC connector, with the alignment fitting perfectly.

 

And on the left enough empty space for the card to fit into the slot ok, those left chips are too close to the edge.

[RickyDean]

13 minutes ago, Gary from OPA said:

Just remember there is two types of PEB, one that has the card slot metal all the way up to the top, as such make sure there enough spacing for the right for the internal FDC connector, with the alignment fitting perfectly.

 

And on the left enough empty space for the card to fit into the slot ok, those left chips are too close to the edge.

The left chips are just there for the reason that they were going to fulfill a purpose later when I redo the board to fit 2 FDC IC's and the buffer chips. When I finish this as a Corcomp 2793 FDC board they will be removed. But then I will move IC's, traces, and components around and will add these back into the footprint for the next board I will be designing. Hence the shape of the board as you see it. The regular CC 2793 board is a bit smaleer and different in shape to this one.

Edited March 22 by RickyDean
spelling

[+MarkB]

Just on the traces, vertical on side and horizontal on the other is generally a good idea but not every trace needs to follow that.  Some traces can just route around others and avoid needing any via.  I see some traces have vias in the middle with no connection to the other side - and some with no connection at all - you can delete these.  If you set a snap to a fraction of the pin pitch you could get the tracks straighter and more parallel.  Some of the traces look a little tightly spaced.  Id also make all traces either 0, 45 or 90 degrees for aesthetics.  Finally consider filling unused areas with copper.  One side ground and the other vcc.  Make the whole board a decoupling cap and do a bit to help the environment by etching less copper and have fewer drills 🙂