AtariGeezer Posted September 20 Share Posted September 20 Here's an update to the 1450xl Parallel Floppy Drive Interface showing the logic gates of the TTL IC's. From this it should be easier for me to create a Final Schematic... 1 Quote Link to comment Share on other sites More sharing options...
Mathy Posted September 20 Share Posted September 20 Hello Lenore You do know that the 1200XL/14x0XL(D) MMU is different from the XL/XE MMU and both are different from the XEGS MMU? Sincerely Mathy 2 Quote Link to comment Share on other sites More sharing options...
+kheller2 Posted September 20 Share Posted September 20 Everyone relax…. A care package is on its way to help. 👍 4 Quote Link to comment Share on other sites More sharing options...
reifsnyderb Posted September 20 Share Posted September 20 (edited) Worst case, strip the MMU down to a minimal form and re-add a little bit of instructions at a time. i.e. Just get a 16k system working first. Edited September 20 by reifsnyderb Quote Link to comment Share on other sites More sharing options...
Dropcheck Posted September 20 Author Share Posted September 20 45 minutes ago, AtariGeezer said: Did I read that you have a loaner built 1450xl correctly? If so, can't you test your PAL's in the loaner? U12 is the MMU, so if that is improperly programmed, that would be a big reason why it's not working... I found a webpage that talks about building an adapter to read the PAL16V8 chip as a 27C020 EPROM in a device programmer. http://dreamjam.co.uk/emuviews/readpal.php Sequence of operations to duplicate a 20 pin protected PAL.pdf 184.58 kB · 0 downloads Then using a program called Logic Friday to convert the read data into the correct equations. Logic Friday for Windowslf114_setup.exe 858.13 kB · 0 downloads Not sure if a TL88 can read a protected PAL directly or not... I only have a bare board right now. kheller2 is trying to get his working 1450XL sent to me. At the very least it will give me good signals to compare my board to. I would love to be able to get a good copy of any of those PALs. Unfortunately that pdf indicates it cannot handle "Registered" PALs like PAL16R4, which is U11. I was hopeful Bob1200XL had managed to dump a good copy of all three. That's why I asked him for the jedec files. Problem is I don't have a PAL programmer. Sooooooo....... tf_hh is working to try to devine a set of working GAL equations based on schematics and a disassembly of the existing PAL jedecs. Quote Link to comment Share on other sites More sharing options...
Dropcheck Posted September 20 Author Share Posted September 20 54 minutes ago, Mathy said: Hello Lenore You do know that the 1200XL/14x0XL(D) MMU is different from the XL/XE MMU and both are different from the XEGS MMU? Sincerely Mathy I'm using the chips specified by Vandal968's BOM for the 1450XL he built up and got working, so the only unknown are the three PAL chips. 🙂 1 Quote Link to comment Share on other sites More sharing options...
AtariGeezer Posted September 20 Share Posted September 20 On 12/11/2023 at 9:52 AM, kheller2 said: I think the "Parallel Disk Controller" schematics are a draft or a different revision from the 1450XLD shortboard schematics. I noticed today an old picture from facebook showed a real 1450 FD schematic. sigh. This one has at least one error, note that pin 16 on the floppy connector is used twice. These schematics were posted previously, above. I think. Do you remember which FB Group you saw these on? Those seem to be for the 1090xl... Quote Link to comment Share on other sites More sharing options...
reifsnyderb Posted September 20 Share Posted September 20 15 minutes ago, AtariGeezer said: Do you remember which FB Group you saw these on? Those seem to be for the 1090xl... Those schematics aren't related to the 1090XL Serial/Parallel document in the picture. Quote Link to comment Share on other sites More sharing options...
AtariGeezer Posted September 20 Share Posted September 20 6 minutes ago, reifsnyderb said: Those schematics aren't related to the 1090XL Serial/Parallel document in the picture. Nope, but the bottom pic is the from the Parallel Disk Controller for the 1090... Found it: 1 1 Quote Link to comment Share on other sites More sharing options...
reifsnyderb Posted September 20 Share Posted September 20 15 minutes ago, AtariGeezer said: Nope, but the bottom pic is the from the Parallel Disk Controller for the 1090... Found it: WOW! I am missing that one! Are there any more?? Quote Link to comment Share on other sites More sharing options...
AtariGeezer Posted September 20 Share Posted September 20 Not that I am aware of. Probably found that on Curt's site before he passed. Will have to search my HD with the same date that was downloaded to see... Quote Link to comment Share on other sites More sharing options...
reifsnyderb Posted September 20 Share Posted September 20 9 minutes ago, AtariGeezer said: Not that I am aware of. Probably found that on Curt's site before he passed. Will have to search my HD with the same date that was downloaded to see... If you find anything, please post it. Thanks! Quote Link to comment Share on other sites More sharing options...
+kheller2 Posted September 20 Share Posted September 20 I was always curious what those schematics were for: a 1090 card, some previous 1450 version, 800XLD, etc. I figured that it might be possible to retrofit the TONG floppy portion but I’m not sure given the complexity of Carmen and Barbara. The 1450 FD Controller schematics have never been posted other than that glimpse on FB. And someone did a reverse schematic design of a wire wrap version here on AA. (I’m still confused if there were two different floppy designs for the 1450 Dynasty project, one certainly used bare 1050 mechs on a production ready looking board). BTW, I have some source code for a 1450 floppy by Mike B. And the 1050CR. I’ll dig those up and post them. 2 Quote Link to comment Share on other sites More sharing options...
_The Doctor__ Posted September 20 Share Posted September 20 the tandon mechs were double sided if the thoughts are still correct. there could have been other ideas coming in the final selections. Quote Link to comment Share on other sites More sharing options...
+kheller2 Posted September 20 Share Posted September 20 5 hours ago, _The Doctor__ said: the tandon mechs were double sided if the thoughts are still correct. there could have been other ideas coming in the final selections. That appears to be correct when looking at this board: Quote Link to comment Share on other sites More sharing options...
AtariGeezer Posted September 20 Share Posted September 20 9 hours ago, kheller2 said: The 1450 FD Controller schematics have never been posted other than that glimpse on FB. And someone did a reverse schematic design of a wire wrap version here on AA. That someone is me See my post above is the latest drawing. Getting closer to the final by using the hand drawn Tong board and the 1090xl Parallel Disk Controller schematics... 1 Quote Link to comment Share on other sites More sharing options...
+kheller2 Posted September 20 Share Posted September 20 35 minutes ago, AtariGeezer said: That someone is me See my post above is the latest drawing. Getting closer to the final by using the hand drawn Tong board and the 1090xl Parallel Disk Controller schematics... Did we ever get a dump of the EPROM on the wire wrap board? I know I have the code for one of these: Quote Link to comment Share on other sites More sharing options...
AtariGeezer Posted September 20 Share Posted September 20 1 hour ago, kheller2 said: Did we ever get a dump of the EPROM on the wire wrap board? I know I have the code for one of these: Those top three ROM Files are for this board (the one I'm reverse engineering) The small board you posted doesn't have ROM'S nor pics of the reverse side *at least what I have seen) Quote Link to comment Share on other sites More sharing options...
+kheller2 Posted September 20 Share Posted September 20 10 minutes ago, AtariGeezer said: Those top three ROM Files are for this board (the one I'm reverse engineering) The small board you posted doesn't have ROM'S nor pics of the reverse side *at least what I have seen) I'm going to assume U6 and U10 are the same images that were at the museum. Pretty sure I have U6 source code and a later revision, see below. The problem with these dates are that they are during the TONG timeline. So, is that wire wrap a photo for the TONG project? Since it connects to a SA400 floppy, I'm going to say yes. And as such, they should match TONG schematics. *** PDD - Parallel Disk Device * * MODS * G. Riker 06/01/83 * MODS * G. Riker 06/01/83 * 1. Fix handler entry points. * R. K. Nordin 03/21/84 * 2. Do not issue initial prompt if door closed. * R. K. Nordin 03/29/84 * 3. a. Change sector read/write routines so they * run faster. * b. Remove support for TOGGLE command. * c. Change highest legal ID from $34 to $38 * d. Remove various bugs. * e. Redefine BITTBL. * f. Remove all code that modifies the DCB (except * for DUNIT, which is restored by PIO). * g. Remove unnecessary conversion routines. * h. Fix the infinite loop caused by interaction * between SIO emulation and interrupt * processing. * i. Modify SIO emulation so it will work on both * PAL and NTSC. * j. On calls to serial bus drives, adjust DUNIT * before passing control to SIO. * k. Set critical I/O flag during status calls. * l. Synchronize WAKEUP with the video system to * avoid undesirable interaction. * Mike Barall 04/03/84 * 4. Change ATTN-BUSY protocol so that the disk controller * does not need to have timeouts on each byte sent * across the parallel bus. * Mike Barall 04/23/84 * 5. a. Remove the code which switches in the modem * device before toggling the ATTN line. A change in * the design of the 1450 motherboard has made this * unnecessary. * b. Bring into compliance with the new parallel * device RAM allocation scheme. * Mike Barall 04/30/84 * 6. Disable interrupts while toggling ATTN. * Mike Barall 05/28/84 PDD Rev. E is based on Rev. D and incorporates a change so that if the latch is closed a boot will be attempted (rather than the drive being ignored). Quote Link to comment Share on other sites More sharing options...
AtariGeezer Posted September 20 Share Posted September 20 13 minutes ago, kheller2 said: I'm going to assume U6 and U10 are the same images that were at the museum. Pretty sure I have U6 source code and a later revision, see below. The problem with these dates are that they are during the TONG timeline. So, is that wire wrap a photo for the TONG project? Since it connects to a SA400 floppy, I'm going to say yes. And as such, they should match TONG schematics. *** PDD - Parallel Disk Device * * MODS * G. Riker 06/01/83 * MODS * G. Riker 06/01/83 * 1. Fix handler entry points. * R. K. Nordin 03/21/84 * 2. Do not issue initial prompt if door closed. * R. K. Nordin 03/29/84 * 3. a. Change sector read/write routines so they * run faster. * b. Remove support for TOGGLE command. * c. Change highest legal ID from $34 to $38 * d. Remove various bugs. * e. Redefine BITTBL. * f. Remove all code that modifies the DCB (except * for DUNIT, which is restored by PIO). * g. Remove unnecessary conversion routines. * h. Fix the infinite loop caused by interaction * between SIO emulation and interrupt * processing. * i. Modify SIO emulation so it will work on both * PAL and NTSC. * j. On calls to serial bus drives, adjust DUNIT * before passing control to SIO. * k. Set critical I/O flag during status calls. * l. Synchronize WAKEUP with the video system to * avoid undesirable interaction. * Mike Barall 04/03/84 * 4. Change ATTN-BUSY protocol so that the disk controller * does not need to have timeouts on each byte sent * across the parallel bus. * Mike Barall 04/23/84 * 5. a. Remove the code which switches in the modem * device before toggling the ATTN line. A change in * the design of the 1450 motherboard has made this * unnecessary. * b. Bring into compliance with the new parallel * device RAM allocation scheme. * Mike Barall 04/30/84 * 6. Disable interrupts while toggling ATTN. * Mike Barall 05/28/84 PDD Rev. E is based on Rev. D and incorporates a change so that if the latch is closed a boot will be attempted (rather than the drive being ignored). Cool, I'd love to see those... Quote Link to comment Share on other sites More sharing options...
Dropcheck Posted Saturday at 04:30 PM Author Share Posted Saturday at 04:30 PM (edited) Found another mystery connection. R151 for Y2 One side ties to pin 8 on Y2 and U25 pin 2. The other side doesn't seem to tie to any thing. Schematic claims it ties to +5V. Not +5V or GND. No trace. 😔 Edited Saturday at 04:30 PM by Dropcheck 1 Quote Link to comment Share on other sites More sharing options...
+kheller2 Posted Saturday at 05:59 PM Share Posted Saturday at 05:59 PM When you are done, you can call yours the X3 revision, since X2 has a lot of errors.. even for 150 units of them. I wish I had kept my 1400XL and could compare its traces. Quote Link to comment Share on other sites More sharing options...
AtariGeezer Posted Saturday at 10:58 PM Share Posted Saturday at 10:58 PM Here are the docs that have the Equations for PAL-A, PAL-B and PAL-C FOR THE 1400XL and should be the same for the 1450xl. Also is a second pdf that has the Equations for the 1450xl MMU Alone... Who here can create the JED files from these??? 1400-PAL_Chips-and-Equations.pdf CO61618A-CMOS-MMU_Chip.pdf 2 Quote Link to comment Share on other sites More sharing options...
Dropcheck Posted Saturday at 11:21 PM Author Share Posted Saturday at 11:21 PM 19 minutes ago, AtariGeezer said: Here are the docs that have the Equations for PAL-A, PAL-B and PAL-C FOR THE 1400XL and should be the same for the 1450xl. Also is a second pdf that has the Equations for the 1450xl MMU Alone... Who here can create the JED files from these??? 1400-PAL_Chips-and-Equations.pdf 1.59 MB · 0 downloads CO61618A-CMOS-MMU_Chip.pdf 510.91 kB · 0 downloads These are very close to what I have traced on the bare board for the PALs. However I am seeing on U7 PAL B pins 16 and 17 seemed to be swapped for the votrax. On U11 PAL C pin 18 does not seemed to be connected. I am re-verifying now. Quote Link to comment Share on other sites More sharing options...
reifsnyderb Posted Sunday at 12:30 AM Share Posted Sunday at 12:30 AM (edited) 1 hour ago, AtariGeezer said: Here are the docs that have the Equations for PAL-A, PAL-B and PAL-C FOR THE 1400XL and should be the same for the 1450xl. Also is a second pdf that has the Equations for the 1450xl MMU Alone... Who here can create the JED files from these??? 1400-PAL_Chips-and-Equations.pdf 1.59 MB · 0 downloads CO61618A-CMOS-MMU_Chip.pdf 510.91 kB · 0 downloads Looks like they are both 16V8's. An ATF16V8B could do it and they are pretty cheap. WinCupl can create the .jed files. Once the docs are confirmed with the board, please let me know. Edited Sunday at 12:44 AM by reifsnyderb 1 Quote Link to comment Share on other sites More sharing options...
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