Vigo Posted November 13, 2003 Share Posted November 13, 2003 Hi, i´d like to know if the following is the truth: Atari super chip games use F6 bankswitching, have 256bytes of ram at $1000-$101ff in all banks, and there is no way to see the ROM data at $1000-$101ff. Is this correct? Quote Link to comment Share on other sites More sharing options...
CPUWIZ Posted November 13, 2003 Share Posted November 13, 2003 Hi, i´d like to know if the following is the truth: Atari super chip games use F6 bankswitching, have 256bytes of ram at $1000-$101ff in all banks, and there is no way to see the ROM data at $1000-$101ff. Is this correct? No, the SuperChip is nothing but a 128byte RAM chip (it contains no bankswitching logic) but you are correct about the location(s). The first 128 bytes of each block are the read area and the second 128 bytes of each block are the write area. When I say block, I mean 4K chunk. Quote Link to comment Share on other sites More sharing options...
Vigo Posted November 13, 2003 Author Share Posted November 13, 2003 Excellent............ Hmmm, do you think it would break compatibility if this whole area can BOTH be read and written to? Quote Link to comment Share on other sites More sharing options...
CPUWIZ Posted November 13, 2003 Share Posted November 13, 2003 Excellent............ Hmmm, do you think it would break compatibility if this whole area can BOTH be read and written to? You can't do that because the 2600 does not have a WE line, hence the 2 seperate locations. Or do you have something else in mind ? Quote Link to comment Share on other sites More sharing options...
Vigo Posted November 13, 2003 Author Share Posted November 13, 2003 Right now, i´m designing my new Atari Development system (AIDA) based around a 6502 CPU, the TIA and 6532, 16KB Ram, 6522 VIA for the parallel port and 8K BIOS EPROM. I´m now designing the CPLD, which will be the heart of the system and be responsible for: - Generating all addresses for the BIOS, RAM, 6522 VIA, TIA and 6532 - Being able to switch between RAM and ROM at $1000 - $1FFF via software - Fallback mode to start Atari 2600 games from ROM and RAM. - Emulating various bankswitching schemes, which can also be software selected. - In native mode, the whole 16K ram can be accessed lineary at $4000-$7FFF Right now i´m designing the bankswitch circuit and trying to figure out how much schemes i can put in by using as less gates as possible. Since this is going to be a new system, i have of course access to all 6502 lines... :-) Quote Link to comment Share on other sites More sharing options...
CPUWIZ Posted November 13, 2003 Share Posted November 13, 2003 Right now, i´m designing my new Atari Development system (AIDA) based around a 6502 CPU, the TIA and 6532, 16KB Ram, 6522 VIA for the parallel port and 8K BIOS EPROM. I´m now designing the CPLD, which will be the heart of the system and be responsible for: - Generating all addresses for the BIOS, RAM, 6522 VIA, TIA and 6532 - Being able to switch between RAM and ROM at $1000 - $1FFF via software - Fallback mode to start Atari 2600 games from ROM and RAM. - Emulating various bankswitching schemes, which can also be software selected. - In native mode, the whole 16K ram can be accessed lineary at $4000-$7FFF Right now i´m designing the bankswitch circuit and trying to figure out how much schemes i can put in by using as less gates as possible. Since this is going to be a new system, i have of course access to all 6502 lines... :-) Nice , although the ability to read and write to both areas won't be of much help in the real world (without your new devkit). Quote Link to comment Share on other sites More sharing options...
Vigo Posted November 13, 2003 Author Share Posted November 13, 2003 To prove i´m talking no bullshit, here is the BIOS file of my old development system. The background is red because on a standard Atari, the ram test fails of course... bios.zip Quote Link to comment Share on other sites More sharing options...
Vigo Posted November 13, 2003 Author Share Posted November 13, 2003 Aber pssst....... Mehr gibt´s hier erst, wenn das Teil fertig ist... Quote Link to comment Share on other sites More sharing options...
CPUWIZ Posted November 13, 2003 Share Posted November 13, 2003 Aber pssst....... Mehr gibt´s hier erst, wenn das Teil fertig ist... Alles Klar. Quote Link to comment Share on other sites More sharing options...
Thomas Jentzsch Posted November 13, 2003 Share Posted November 13, 2003 Hmmm, do you think it would break compatibility if this whole area can BOTH be read and written to? A few games may not work anymore then. I have seen sourcecode where writes to ROM happened just to waste some cycles. Maybe modifying an emulator and test some games is the easiest way to find out. PS: Das Bios sieht schonmal sehr vielversprechend und gut aus. Echt nette Grafik! Ach ja, ist eigentlich völlig unwichtig, aber der PAL Standard sind 312 Zeilen. Quote Link to comment Share on other sites More sharing options...
Vigo Posted November 14, 2003 Author Share Posted November 14, 2003 I think the problem is now solved, since my alpha design now should behave like a real Superchip. Danke für die Blumen! Hehe, das hab ich gestern beim Start mit Z26 auch gemerkt. Das BIOS wurde nämlich nur mit Hilfe meines Devkits entwickelt, und da haben sich aus lauter Eifer wohl 2 Zeilen zuviel eingeschlichen..... Quote Link to comment Share on other sites More sharing options...
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