cschell Posted December 31, 2004 Share Posted December 31, 2004 Hi, I don't recall what thread I last posted this in, and a search for techdocs didn't show up, so I'm going to be lazy and make a new topic. Anyway, I have upated the CC2 techdocs.txt file I posted long ago. Pretty much complete at this point. http://www.schells.com/techdocs.txt Does it inspire anyone enough to want to do something? I'm still debating on posting the OS source code. I spent some time this week trying to get a way that people could make their own bankswitching files. I tried BYU electric which claims to create the proper EDIF files, but it didn't. I then tried Icarus Verilog. It's a lot closer, but needs to have a Spartan module created. I think the LPN model could be modified to do this for not overly complicated setups. (It wouldn't be all that efficient as it doesn't know about the specific hardware of the Spartan FPGA.) Anyway, when I tried to build the Icarus compiler it failed so I gave up. (And people would have to learn Verilog.) Another option is the Xilinx abl2edif program. It's free and I'm assuming that it can be used to create bankswitching files in Abel, although I didn't really look into it. Does anyone care about any of this? Chad Quote Link to comment Share on other sites More sharing options...
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