Question about 'plp' and 'php'

[vdub_bobby]

What, exactly, do php and plp do?

 

Would this code...

php

pla

sta ZP

Put the entire processor status register in a zero-page memory location?

 

And would this...

lda ZP

pha

plp

Set the processor status register to whatever was in the zero-page memory location?

[Robert M]

Yes, you are correct in both cases.

[Thomas Jentzsch]

Almost, but the zero-flag will be always set after PLA.

 

But you can do this:

ldx #ZP

txs

...

php

and later:

ldx #ZP   

txs    ; optional

plp

[Thomas Jentzsch]

Correction: the Z-flag will be never set.

[vdub_bobby]

Almost, but the zero-flag will be always set after PLA.

 

But you can do this:

ldx #ZP

txs

...

php

and later:

ldx #ZP   

txs    ; optional

plp

 

That makes sense...I think.

 

Are you saying that after this:

php

pla

sta ZP

 

The processor status register stored in ZP may or may not match the actual processor status register because the 'pla' modifies the processor status register?

 

Is that because 'pla' sets the zero-flag based on what value is pulled into A? (Does 'pla' also modify the sign flag?) And the processor status register will never be zero?

 

But what if you did this...

lda #0

pha

plp

php

pla

Wouldn't the zero flag then be...um...set? I think?

[Thomas Jentzsch]

Is that because 'pla' sets the zero-flag based on what value is pulled into A?  (Does 'pla' also modify the sign flag?)  And the processor status register will never be zero?

Even if it might be zero, then the zero-flag wasn't set before and the result is wrong again.

 

There is no problem with the sign-flag, because it is stored in bit7, which sets the flag when the flag was set before.

 

But what if you did this...

lda #0

pha

plp

php

pla

Wouldn't the zero flag then be...um...set?  I think?

Hm, according to my tests with z26, the result is $30. So the unused flag in bit5 is always set, and the break flag (bit4) seems to be set too.

 

Therefore the answer is no.

[vdub_bobby]

Thanks.

[Nukey Shay]

Why would you want to store the processor status in a zero page location? It would be better to just php, and plp later when you need it (or reorganize the routine so that it's not needed at all).

 

Have an example of what you are attempting?

[Bruce Tomlin]

Correction: the Z-flag will be never set.

For those who don't do Zen, this is because one of the bits of the P register is always set to 1. PLA sets the Z and N flags based on what value is read into A. Since this value is never zero, the Z flag will never be set after this particular code.

 

(The B flag should be set too, as it's only pushed as 0 in response to an interrupt.)

[vdub_bobby]

Why would you want to store the processor status in a zero page location?  It would be better to just php, and plp later when you need it (or reorganize the routine so that it's not needed at all).

 

Have an example of what you are attempting?

 

Not attempting anything...I haven't even thought of a situation where I might need to do this. Just curious, that's all

 

(The B flag should be set too, as it's only pushed as 0 in response to an interrupt.)

 

Hm, according to my tests with z26, the result is $30. So the unused flag in bit5 is always set, and the break flag (bit4) seems to be set too.

This is what I don't understand. So you can't manually clear the break flag (with a plp)?

[Bruce Tomlin]

The B flag in the P register is meaningless. Only the stacked value of the P register matters. Whenever it is written to the stack, the value written is entirely dependent upon whether a BRK instruction was executed or not. In fact, there might not even actually be a B flag in the P register itself.