had the 7800 launched in 1984....

[GroovyBee]

Theres an echo in here!

[GameGirl420]

That would have been interesting. An NES with an Atari logo on it I read in a book called History of Video Games that alot of people at Atari hated Japanese games. Which is why Pacman for 2600 came out so crappy.

Edited June 9, 2009 by lushgirl_80

[kool kitty89]

Nah, that was just the particular programmer, and was Pacman specifically, not JP games in gereral iirc. (look how well Space Invaders turned out, for example)

 

But this idea about Atari buying Nintendo is just dumb, in 1984 they were in the pit of the video game crash and Warner had been looking for a way out, and found it with Tramiel. Now Warner could have possibly been in a position to buy out, absorb, or get specific rights with Nintendo in America after dumping Atari, though I doubt a total buy-out would be accepted. Remember Nintendo was doing well with their system in Japan, launched in 1983. (and Sega's SG-1000 was doing poorly)

Atari itsself, under Warner or (especially) Tramiel, would be in no position to buy out Nintendo, actually it could have been the other way arround (N buying Atari off Warner's hands), and Nintendo may have considdered it, but Atari's name was soiled to retailers due to the crash, thus there wasn't too much of a point. (though the brand certainly still held a lot of weight in the public, so there would be that advantage)

 

This latter bit is much more conceivable (though again a mixed bag as there's Atari's debt and soiled rep with retailers), it's still weird to think of though, Atari becoming Nintendo of America.... Yeah that's defintely an odd one. (an , of course the 7800 would never be fully launched, possibly the 2600 Jr. as a budget machine as it wouldn't be in direct competition with the Famicom/NES/"AES" and Atari's 8-bit computer linewould still be profitable, and certainly not in direct competition with Nintendo's system)

[DracIsBack]

This latter bit is much more conceivable

 

I think you're thinking that Nintendo is bigger than it actually was in 1983. It was still VERY small. Famicom was doing alright and Donkey Kong was a hit but it was in no position to buy and run a business the size of Atari.

[kool kitty89]

So Tramel Technology was in a better position than Ninrendo? (I'm talking 1984 here)

[supercat]

If Maria is on a separate bus, then it needs access to graphics without interrupting the 6502. There's 2 solutions for that:

 

What were the timing limitations for simple multiplexer-based logic in those days? Would it have been practical to interleave CPU accesses and display accesses on the cartridge bus without needing double-speed memory, if the code and display data were fetched from different memory arrays? For example, assume the CPU is running at 2MHz and there is a 12MHz clock.

 

At step 0, drive phi0 to the CPU and start driving the CPU address to the chip. The data bus will hold the last byte of CPU data.

At step 1, have the chip latch the address, and start outputting the LSB of the last requested byte of display data.

At step 2, drive a new display address to the chip. At the end of this step, latch the data bus into the display controller.

At step 3, hold the address. Have the chip start outputting the MSB of the last requested byte of display data.

At step 4, hold the address. At the end of this step, latch the data bus into the display controller.

At step 5, hold the address. Have the chip start outputting the requested CPU byte.

 

The CPU memory will have a valid address by the end of step 1, and will have until the end of step 4 to supply data, so it would have at least a full half cycle (it would likely have the address sooner, and could likely supply the data later). The display memories (MSB/LSB) would have even longer to supply their data. If one were using off-the-shelf parts in the cartridge, one would have to use three separate ROM chips plus some glue logic. Integrating the three ROMs into one chip, however, shouldn't be a problem.

 

OTOH, using a separate bus wouldn't be evil either. A "chevron-shaped" cartridge slot would have allowed 7800 cartridges to have many more pins while still having 2600 carts fit nicely.

[DracIsBack]

So Tramel Technology was in a better position than Ninrendo? (I'm talking 1984 here)

 

Nintendo was a *very* small company in 1983/4 and would not have had the resources to "take over" Atari as you suggest.

[gdement]

If Maria is on a separate bus, then it needs access to graphics without interrupting the 6502. There's 2 solutions for that:

 

What were the timing limitations for simple multiplexer-based logic in those days? Would it have been practical to interleave CPU accesses and display accesses on the cartridge bus without needing double-speed memory, if the code and display data were fetched from different memory arrays? For example, assume the CPU is running at 2MHz and there is a 12MHz clock.

 

At step 0, drive phi0 to the CPU and start driving the CPU address to the chip. The data bus will hold the last byte of CPU data.

At step 1, have the chip latch the address, and start outputting the LSB of the last requested byte of display data.

At step 2, drive a new display address to the chip. At the end of this step, latch the data bus into the display controller.

At step 3, hold the address. Have the chip start outputting the MSB of the last requested byte of display data.

At step 4, hold the address. At the end of this step, latch the data bus into the display controller.

At step 5, hold the address. Have the chip start outputting the requested CPU byte.

 

The CPU memory will have a valid address by the end of step 1, and will have until the end of step 4 to supply data, so it would have at least a full half cycle (it would likely have the address sooner, and could likely supply the data later). The display memories (MSB/LSB) would have even longer to supply their data. If one were using off-the-shelf parts in the cartridge, one would have to use three separate ROM chips plus some glue logic. Integrating the three ROMs into one chip, however, shouldn't be a problem.

 

OTOH, using a separate bus wouldn't be evil either. A "chevron-shaped" cartridge slot would have allowed 7800 cartridges to have many more pins while still having 2600 carts fit nicely.

 

You know much more about hardware than I do.

It sounds like carts described above might be significantly more expensive than a single standard ROM, but still it's more future-proof than being limited to a fixed amount of display RAM in the console. And I imagine a custom integrated chip might make it cheaper if they do enough volume.

[kskunk]

What were the timing limitations for simple multiplexer-based logic in those days? Would it have been practical to interleave CPU accesses and display accesses on the cartridge bus without needing double-speed memory, if the code and display data were fetched from different memory arrays? For example, assume the CPU is running at 2MHz and there is a 12MHz clock.

 

The display memories (MSB/LSB) would have even longer to supply their data. If one were using off-the-shelf parts in the cartridge, one would have to use three separate ROM chips plus some glue logic. Integrating the three ROMs into one chip, however, shouldn't be a problem.

 

You've just invented the Neo Geo cartridge bus. Sadly, Neo Geo carts aren't cheap, and the multiplexed bus is one of the reasons. Although some Neo Geo carts use high speed TTL, many use PALs or ASICs to do the multiplexing. None use custom (or 'integrated') ROMs.

 

High speed TTL existed in 1984 but it burned a lot of watts and you'd need several chips. Even in 1984, the 8MHz VIC-II in the Commodore 64 was on its second heat-reduction redesign, and still sported a large heat sink. Not something you'd want in a small cart! You could use PALs or ASICs like the Neo Geo, but implementing several multiplexed buses on one chip requires an expensive high pin count package, potentially more expensive than the ROMs.

 

Custom ROMs seem like a good idea but there's a reason they rarely show up in cartridges. Mask ROMs were so cheap in 1984 because they were commodities. Dozens of manufacturers made them, all competing for the lowest possible price. Thus mask ROM processes were tweaked for very high yields and high density, at the expense of speed and logic gate size. There are not enough layers on a mask ROM process to do anything faster or larger than a multiplexer.

 

You can put ROM on a high speed logic process, but because there are more layers and process steps, the yields are lower and the manufacturing time is higher. A larger more expensive manufacturing line is required, and generally logic lines are not set up to rapidly change masks, whereas commodity mask ROM lines can make a different cart every hour.

 

Finally, most console makers allowed 3rd parties to make their own cartridges. 3rd parties could shop around for the lowest bidder using commodity ROMs, contracting exactly the right price at the right quantity with the right lead times. Requiring people to purchase their ROMs through Atari's custom process is not very appealing, especially during the holidays when the line is booked solid with Atari's own projects...

 

- KS

[kool kitty89]

You know much more about hardware than I do.

It sounds like carts described above might be significantly more expensive than a single standard ROM, but still it's more future-proof than being limited to a fixed amount of display RAM in the console. And I imagine a custom integrated chip might make it cheaper if they do enough volume.

 

He is the one that pointed out the reason interleaving wan't a good option either.

 

The cart's he describes would still only be using a single circuit board, but presumably with prong like portions of the board containing additional connectors, sot of like the extra ones used on some enhanced SNES carts. (granted these only added 12 pins)

 

I actually considdered this myself, but there's a problem. Doesn't the 2600 slot have prongs to unlock the built-in dust covers on the Atari produced 2600 carts? Without these you'd loose the compatibility, and these plastic prongs are located in the same place as the proposed added cart connectors would go... (inless you made the carts super wide to compensate for this as well)

 

 

The main reason I mentioned a seperate bus for Maria would be to keep it from being slowed down by having to share the bus with the CPU, though with slower DRAM, I don't know how much of an advantage this would be over shared SRAM. (plus there's the speed issue of the CPU feeding graphics data after reading the ROM, instead of MARIA having acces to the ROM itsself)

 

The option of simply adding more SRAM might be interesting, it was braught up that using a single 8K SRAM instead of the par of 2K ones would save space as well. (I'm not aware of what other IC sizes would be available, but no 4K SRAMs weren't available?) Of course this could add to cost, depending on the relative cost of the 2K and 8K chips, and if there would be significant savings from having one less chip on the board. (or course adding a POKEY would effect this as well)

 

DRAM is cheaper, but slower and requires the refresh circuitry, so would the system be worse off with say 16K of shared DRAM in place of the 4K of SRAM?

 

 

 

Also, what are you guys thoughs on the joypads for the 7800, should they have been used in the US as standard, replacing the proline sticks, probalby keeping the prolines available as accessories for those that prefer them. (though I think most games that are better with joysticks would probably play better with the CX-40 anyway, particularly Robotron in dual stick mode)

Edited June 10, 2009 by kool kitty89

[DracIsBack]

Also, what are you guys thoughs on the joypads for the 7800, should they have been used in the US as standard, replacing the proline sticks, probalby keeping the prolines available as accessories for those that prefer them. (though I think most games that are better with joysticks would probably play better with the CX-40 anyway, particularly Robotron in dual stick mode)

 

I don't find either particularly comfortable but essentially "learned to live" with both. For most games, I find the joypad easier. One thing is that I don't find it's as sensitive as the proline. When doing "the jump from hell" in SCRAPYARD DOG in one of the early sewer levels (2-3, I think), I can only pull it off with a PRO-LINE.

[Gregory DG]

I think Atari's problem is that they had too many arcade ports that had been rehashed numerous times already and not enough original "WOW!" type games. I mean, what's the ratio of arcade ports to original titles on the 7800 anyway?

[GroovyBee]

I mean, what's the ratio of arcade ports to original titles on the 7800 anyway?

Its increasing slowly every day!

Edited June 10, 2009 by GroovyBee

[cybercylon]

So Tramel Technology was in a better position than Ninrendo? (I'm talking 1984 here)

 

Nintendo was a *very* small company in 1983/4 and would not have had the resources to "take over" Atari as you suggest.

 

I suspect that is one of the reasons why Nintendo approached Atari in the first place to market the NES.

[gdement]

The main reason I mentioned a seperate bus for Maria would be to keep it from being slowed down by having to share the bus with the CPU, though with slower DRAM, I don't know how much of an advantage this would be over shared SRAM. (plus there's the speed issue of the CPU feeding graphics data after reading the ROM, instead of MARIA having acces to the ROM itsself)

Given that the Maria can now run full time, in practical gameplay the RAM speed might not be any loss compared to the shared bus. But I don't know exactly how much slower the DRAM would be. Meanwhile you gain usable CPU cycles.

 

Presumably you'd only upload graphics to the Maria at convenient times, like in between screens or levels.

One issue with dedicated Maria RAM is they'd need to revise the "holey DMA" concept. The existing scheme would put major limitations on half the RAM. With shared memory you can just use it for something else instead of graphics.

 

 

The option of simply adding more SRAM might be interesting, it was braught up that using a single 8K SRAM instead of the par of 2K ones would save space as well. (I'm not aware of what other IC sizes would be available, but no 4K SRAMs weren't available?) Of course this could add to cost, depending on the relative cost of the 2K and 8K chips, and if there would be significant savings from having one less chip on the board. (or course adding a POKEY would effect this as well)

For whatever reason, SRAM only comes in multiples of 4: 2KB, 8KB, 32KB etc. That's also why Wint/Summer Games carts have a 32KB SRAM in them, even though only 16KB is addressable.

I'd be curious about the quantity price of an 8KB SRAM vs a pair of 2KB in 1983/84.

 

DRAM is cheaper, but slower and requires the refresh circuitry, so would the system be worse off with say 16K of shared DRAM in place of the 4K of SRAM?

With shared memory, I think a larger DRAM would be good for the 6502's benefit with more complex games, but it wouldn't do the Maria any good.

With shared access to the ROM, the Maria only needs RAM for display structures but not the graphics themselves. The slower memory would reduce the number of objects it could render, making detailed backgrounds more difficult.

[kool kitty89]

I don't find either particularly comfortable but essentially "learned to live" with both. For most games, I find the joypad easier. One thing is that I don't find it's as sensitive as the proline. When doing "the jump from hell" in SCRAPYARD DOG in one of the early sewer levels (2-3, I think), I can only pull it off with a PRO-LINE.

 

Ah, do you prefer to use the CX-40 for most single button games? (and do you have the screw-in thumbstic for the joypad?)

 

Have you tried the Flashback's mini 7800 controller, it seems like it might be a bit more comfortable? (I think it's compatible with the 7800, though I'm not quite sure if they wired button 2 the same way...)

 

For whatever reason, SRAM only comes in multiples of 4: 2KB, 8KB, 32KB etc. That's also why Wint/Summer Games carts have a 32KB SRAM in them, even though only 16KB is addressable.

I'd be curious about the quantity price of an 8KB SRAM vs a pair of 2KB in 1983/84.

 

I was noticing this trend when looking at various refrences to RAM IC sizes, though I hadn't seen any specfics on it. Is the same thing true for DRAM? Reading several articals and a cfew discussions it seems to imply this, and the charts here: http://phe.rockefeller.edu/LogletLab/DRAM/dram.htm only show IC's of 4, 16, 64, 256K, 1, 4, 16, and 64M. (so it would seem the same 4x multiple, albeit starting a 1 or 4, rather than 2)

Edited June 10, 2009 by kool kitty89

[gdement]

I was noticing this trend when looking at various refrences to RAM IC sizes, though I hadn't seen any specfics on it. Is the same thing true for DRAM? Reading several articals and a cfew discussions it seems to imply this, and the charts here: http://phe.rockefeller.edu/LogletLab/DRAM/dram.htm only show IC's of 4, 16, 64, 256K, 1, 4, 16, and 64M. (so it would seem the same 4x multiple, albeit starting a 1 or 4, rather than 2)

 

I don't know about the really old DRAM, but they definitely have powers of 2 on modern computer SDRAM. For example, you can get a 256MB module with:

8x 32MB chips

16x 16MB chips

32 (normally 36 for ECC) 8MB chips

 

The last option is only JEDEC legal if it's buffered memory, so you don't normally see it with consumer RAM.

 

 

I vaguely remember a college instructor explaining that powers of 4 are more convenient, but I don't remember what the reason was.

[DracIsBack]

Ah, do you prefer to use the CX-40 for most single button games? (and do you have the screw-in thumbstic for the joypad?)

 

No, I've kind of learned how to deal with the prolines and joypads over the years. Reality is that I don't like CX-40 much either (too stiff). I used to use an Epyx 500jx joystick on 1 button games.

 

Have you tried the Flashback's mini 7800 controller, it seems like it might be a bit more comfortable? (I think it's compatible with the 7800, though I'm not quite sure if they wired button 2 the same way...)

 

I don't think they are compatible. The Flashback is actually an NES on-a-chip under the hood.

[kenfused]

One issue with dedicated Maria RAM is they'd need to revise the "holey DMA" concept. The existing scheme would put major limitations on half the RAM. With shared memory you can just use it for something else instead of graphics.

You should be able to put your background tiles into the holey dma areas. Holey DMA is not supposed to apply to character indirect mode IIRC.

 

--Ken

[kool kitty89]

No, I've kind of learned how to deal with the prolines and joypads over the years. Reality is that I don't like CX-40 much either (too stiff). I used to use an Epyx 500jx joystick on 1 button games.

 

Ah, I see. I often end up using the CX-40 joystick as a thumbstick (right thumb on the stick, left on the button), I kind of though this was from habbit, using gamepads growing up (though I had an analog Joystick for PC games), but I later discovered this is how my mom, uncles, and granpa used to use the joysticks on their Atari back in they got it, well before the days of Nintendo. (technically the Vectrex was eariler then Nintendo -even the Famicom- and it's controller seems to be orinted for thumbs as well)

 

I don't think they are compatible. The Flashback is actually an NES on-a-chip under the hood.

Right, I wasn't thinking, they probably use the NES/SNES interface logic. (it's frustrating that some unrelated clone systems do this, including some dedicated Sega Genesis ones, instead of using the original interface -compatible with the original controlers) Though this could mean that some of those other clone systems using DE-9 ports will have bcompatible controllers with the flashback.

 

Of course the flashback 2 uses actual Atari compatible hardware (TIA, RIOT, and 6507 consolidated into an ASIC), so that's a different situation. (there are even soldering points inside to facilitate the addition of a cartridge port)

 

I don't know about the really old DRAM, but they definitely have powers of 2 on modern computer SDRAM. For example, you can get a 256MB module with:

8x 32MB chips

16x 16MB chips

32 (normally 36 for ECC) 8MB chips

 

The last option is only JEDEC legal if it's buffered memory, so you don't normally see it with consumer RAM.

Yeah, I noticed my PC's 512 MB DDR card had 16 chips on it, meaning they were 32 MB each (Each IC being 4-bit, combining to a 64-bit data bus?).

Anyway this may be different than asynchronous DRAM, as you mentioned this example is SDRAM.

Edited June 11, 2009 by kool kitty89

[kskunk]

I vaguely remember a college instructor explaining that powers of 4 are more convenient, but I don't remember what the reason was.

 

The circuit that makes up a DRAM 'bit' is roughly square, since one of the limiting features is usually the wiring matrix, which is the same size for both rows and columns. Due to the optics used, the largest chip you can make is a square. Finally, using a non-power-of-2 number of rows or columns is not really an option in a standard DRAM design.

 

When you add all of that up, it means the largest chip you can make is always 2 * 2^X megabits, which is why each new generation of chips (each new X) has 4 times the bits of the previous.

 

Now, if you make a rectangular chip instead of a square chip, you can get the half size you want. And indeed there are a few rectangular chips nowadays in high volume applications like video cards and DIMMs.

 

In the 80s, DRAM technology was moving so quickly that the latest generation of chips always sold for a premium while the older generation became very cheap very fast. Because of that, it was almost always cheaper to buy two chips from generation X-1 than a half-size chip from generation X. So there was basically no way to make money selling half-size chips. Thus you didn't see many.

 

- KS

[gdement]

Yeah, I noticed my PC's 512 MB DDR card had 16 chips on it, meaning they were 32 MB each (Each IC being 4-bit, combining to a 64-bit data bus?).

It's probably 2 separate logical rows of 8-bit chips (32Mx8) - only 8 chips would be active at the same time. I think the JEDEC standard is no more than 9 chips in a row unless it's registered memory. You may notice when the BIOS is booting it will detect 2 rows of memory for that one module.

Some disreputable memory violates that by using 4-bit chips, but any major brand won't build DIMMs that way (again, unless it's a registered type).

[kool kitty89]

When you add all of that up, it means the largest chip you can make is always 2 * 2^X megabits, which is why each new generation of chips (each new X) has 4 times the bits of the previous.

 

- KS

 

Why do SRAM IC's, as were listed previously, 1/2 the size of comperable DRAM chips? (does SRAM use exactly 2x the Silicon as DRAM)

[mcjakeqcool]

Had the 7800 launched in 1984, Atari would still be the top company in the games industry and the world would be a better place.

[kskunk]

Why do SRAM IC's, as were listed previously, 1/2 the size of comperable DRAM chips? (does SRAM use exactly 2x the Silicon as DRAM)

 

SRAM uses 4-6 times the silicon as DRAM, so at least in raw materials, it is 4-6x more expensive per bit.

 

SRAM is most commonly sold 'square' (in 2 * 2 ^ X increments), just like DRAM. The previous poster was listing kilobytes, not kilobits. So 8KB = 64Kb, 32KB = 256Kb -- just like DRAM, it started at 1Kb and went up 4x per generation.

 

In the early 80s, SRAMs were usually sold in kilobytes while DRAMs were usually sold in kilobits. This is because SRAMs usually had 8 data bins, so they could be addressed a byte at a time, whereas DRAM chips only had one data pin, so you need 8 DRAM chips to make a byte-wide bus. By 1985 or so, 4-bit wide DRAMs started to become popular, but they were still sold by the kilobit, not the kilonybble.

 

- KS