VBXE2 Core DevPack project has started

[candle]

Hi

At Glucholazy 2010 there was a decision, to release some dev-pack for FPGA core developers interested in developing new cores for VBXE

 

for now there is no publicly available release, but i wanted to make an annoucment that there is work in progress, and would happly see some input from Your side

 

i've started this today, and so far i have basic IO functions, PHI2 synchronization, and very preliminary GTIA emulation (only lo-res (4 colour) mode), without any sprites, collision detection or priorities - this was intended as Video DAC usage exaple, so i would not expect it will develop into full GTIA with this core

 

 

this example was written in VHDL because i happend to know this language

if someone has some wishes (within reasonable limits) regarding content of such example i would like to hear about them

 

just remember that this example is not intended for learning VHDL, just for explaining basics concepts for clock domain synchronisation or video memory interface

[+orpheuswaking]

Yeah, what he said

[flashjazzcat]

LOL.

[Rybags]

I was actually thinking the other day... since VBXE in GTIA only mode would appear to have plenty of free space to do other stuff:

 

A 130XE "Freezer emulator" mode, where the VBXE keeps a shadow copy of RAM and the Hardware Register writes within it's own RAM.

 

Would be cool for debugging purposes of software on the real hardware.

 

 

Of course, I still have my wish-list for full VBXE mode - top of the list would be more complex maths stuff, and a table-lookup style blit where source data is used as an index into a table of which data is fetched and stored.

[flashjazzcat]

I think a jpeg (de)compression routine in the VBXE firmware would be a useful addition.

[Rybags]

Problem is... it'd probably take up most of the core... and not real useful if you're not in VBXE graphics mode.

 

But, can't we boot other cores on the fly? Although the obvious problem there is that any software would have to rely on the machine having the cores it needs present.

[+orpheuswaking]

Can someone program my core to do my laundry and the dishes?

[candle]

yes, vbxe can boot any core - off flash and on flash in the fly - for flash boot it takes only 150ms to do this, for off flash a bit longer, a minute perhaps

[Rybags]

So, non flash = uploaded on the fly from the Atari?

[candle]

yep

serial protocol, 92028 bytes to send bit by bit

[Rybags]

So... in theory we could maybe develop partial "system emulation" that could cover other platforms such as VIC-2, ZX-Spectrum, etc?

[+Stephen]

So... in theory we could maybe develop partial "system emulation" that could cover other platforms such as VIC-2, ZX-Spectrum, etc?

I was going to suggest creating the VIC2 but didn't want to start World War 3.

 

I will keep my request somewhat simple - a fast general purpose line draw routine, and maybe a solid shader. Would a fast hardware divide/multiply unit cost too much?

[candle]

it would not, but you can find most of this and much more at opencores.org and similiar sites

[+Stephen]

it would not, but you can find most of this and much more at opencores.org and similiar sites

I know nothing about hardware design or VHDL. I'm fascinated by it, but never took the plunge and tried anything.

[+orpheuswaking]

it would not, but you can find most of this and much more at opencores.org and similiar sites

I know nothing about hardware design or VHDL. I'm fascinated by it, but never took the plunge and tried anything.

 

Still doesn't help me with my laundry or dishes

[candle]

there are some nice explanations and basics covered here and there all over the net - all you really need is a will to learn

 

for example, this is verry basic GTIA emulation:

GTIA_Registers:	process(RUN,CLK_IN,PCNT,RWL,Atari_Adr)
begin
if falling_edge(CLK_IN) and RUN='1' and PCNT="110" then
	case Atari_Adr is
		when x"D016" => COLPF0 <=D;
		when x"D017" => COLPF1 <=D;
		when x"D018" => COLPF2 <=D;
		when x"D019" => COLPF3 <=D;
		when x"D01A" => COLBAK <=D;
		when others => null;
	end case;
end if;
end process;

Atari_GTIA:	process(RUN,CLK_IN,PCNT,AN)
begin
if RUN='1' then
	if falling_edge(CLK_IN) and PCNT(1 downto 0)="10" then
		if AN(2)='0' then
			Color<=COLBAK;
		elsif AN="100" then
			Color<=COLPF0;
		elsif AN="101" then
			Color<=COLPF1;
		elsif AN="110" then
			Color<=COLPF2;
		elsif AN="111" then
			Color<=COLPF3;
		end if;
	end if;
end if;
end process;

lookup_inst	:	lookup PORT MAP (
	address	 => Color,
	inclock	 => CLK_IN,
	outclock	 => CLK_IN,
	q	 => RGB
);

R<=RGB(6 downto 0);
B<=RGB(13 downto 7);
G<=RGB(20 downto 14);
CCLK<=CLK_IN;

 

first process takes care of getting color values from cpu to emulated GTIA, next one decodes AN0-AN2 signals to position in lookup table defined below, the very end of this code outputs decoded RGB values from lookup table to video DAC

Edited August 12, 2010 by candle

[ctirad]

How much complicated is the complete GTIA core? Would be possible to fit it in the CPLD? I'm not much interested in the VBXE, but I'd love to have a GTIA replacement with a RGB or rather YPbPr output.

[Rybags]

GTIA is only partial since the existing GTIA stays put.

 

So, Trigs, legacy collision detection and probably some other stuff isn't in there... although Priority is emulated which would obviously share common logic with collision detection.

[ctirad]

GTIA is only partial since the existing GTIA stays put.

 

I see. I have only a little knowlenge of that ANTIC/GTIA stuff, so I though the later one is used just for video generation.

 

So the new question is: How much complicated is the core of the GTIA subsystem responsible for the video generation?

[Rybags]

If you were to put a number to it... I'd say 60/40 Antic vs GTIA.

 

Antic does most of the pre-processing stuff and feeds the Playfield to GTIA as 8 possible instructions over the AN0-AN2 bus. GTIA then just has to overlay the PMGs, decide priorities and output the final colour.

Complexity? I reckon the priority/collision stuff might be the most complexity but other guys who've looked at schematics might disagree. If you disregard PMGs, then Antic could probably have done the entire video generation job itself with just a little bit more silicon.

 

Did you follow that other thread - I don't have the link here. The alternative for generating RGB or Component could be to take the luma as 4-bit digital input from GTIA, and calculate the colour based on the phase delay coming from GTIA's colour signal output (it can shift through any of 16 possibilities in a half machine clock).

Then with those 2 values in hand, just have a table-lookup to decide on your RGB values.

 

That might be a cheaper route to getting RGB or component from a stock machine, but of course a swap-in board/chip taking the place of GTIA would probably be much less intrusive, requiring less modification.

Edited August 13, 2010 by Rybags

[candle]

current GTIA core is 800LE which is too big for any CPLD i know of

[nichtsnutz]

Hello candle,

 

although I do not own a VBXE I find the posibilities that this hardware has very nice! If the core developement is going to be opened I would think about to also order one.May I ask if you would like to explain a little bit more the clock distribution on the VBXE ? Also the generation of the CSYNC ?

I took a quick look at the VBXE2 schematics and I think as follow:

 

- 14.1875MHz are output from the Atmel and go to the VBXE2 as a main clock.

- The 3.5MHz from the LS393 divider replace the GTIA main clock,so all things are synchronous.

- GTIA outputs FPHI0 to the ANTIC that is also routid to the FPGA.

- The ANTIC outputs PHI0 as the CPU clock and this is also routed to the FPGA,also PHI2 from the cpu.

- ...

 

I do not see any CSYNC output out of the FPGA,but the Atmel has one CSYNC signal.Is the Atmel generating the CSYNC or

is it taken from the original GTIA ?

 

The PCNT signal in you VHDL code seems to count 14.1875MHz / 8 = 1.77MHz so you have 8 cycles for every CPU cycle to synchronize on ?

 

 

I an sorry if I ask to much,I am interrested in the hardware.I had done some timing analysing on the ANTIC some time ago,but I do not think this would be interresting for the most of you here but I definitely would like to see the whole XL on a DE0/1 or a Xilinx eval board,but this is hard work to do to get all the timing right.At the time I have the XL not connected because I mess around with my VC7800 trying to reverse some MARIA timings...

 

Greetings,

Vassilis

 

PS: The image shows an exerpt from the ANTIC ANx timing.The ANx can be sampled with the falling_edge of the FPHI signal.I think ANTIC outputs the ANx with the rising_edge...

[Rybags]

CSYNC for VBXE video is still taken from the GTIA-derived signal.

 

GTIA can autonomously generate horizontal timing, which Antic can override.

 

CSync is actually VSYNC XOR HSYNC. In the offscreen (vertically) period, Antic just sends a long HSYNC command, then VSYNC for 3 scanlines, followed by a long HSYNC again until the display starts.

 

GTIA retains the HSync timing in that period, and the XORing gives the required return from Sync to Blanking level on the video signal during the 3-scanline VSync.

[candle]

there is state machine that is responsible for synchronisation of PCNT counter with falling edge of phi2

 

-------------------------------------------------------------------------
-- Clock_Sync:
--  we need to find edge of phi2 singal using phi0 as reference
--  Atari computers tend to have propagation delays depending on
--  hardware configuration, which sometimes leads to unforseen problems
-------------------------------------------------------------------------
clock_sync:		process(CLK_IN,PHI0,RSTn,SSM)
begin
if RSTn='0' then						-- this is the case when reset button is pressed
	RUN<='0';
	SSM<="00";
	PCNT<="000";
else
	if falling_edge(CLK_IN) then
		case SSM is
			when "00" =>				-- wait for PHI0, as PHI2 is not reliable
				if (PHI0='1') then SSM<="01";
				end if;
			when "01" =>				-- first case of PHI0 found, now we need it preset at next 14mhz cycle
				if (PHI0='1') then SSM<="10";
				else SSM<="00";			-- no? then start over again
				end if;
			when "10" =>				-- two 14mhz cycles with PHI0=1 were found, now we need to find the edge
				if (PHI0='0') then SSM<="11";
				end if;
			when others =>				-- edge found, this will become our referece for phi2 phase
				RUN<='1';
				PCNT<=PCNT+1;
		end case;
	end if;
end if;
end process;

Edited August 13, 2010 by candle

[nichtsnutz]

Hello all,

 

thank you Rybags and candle for the reply.I have thought that you will have to do some synchronization because of the delays.Thank you for sharing the code.Also thank you Rybags for the explanation,this seems logical.I had also measured some of the behaviour you explained also.I think the best way to really understand the GTIA would be to connect it to an external circuit.

Anyway,the posibilities with at runtime loadable hardware would be big with or without GTIA emulation!

 

Greetings,

Vassilis

Edited August 13, 2010 by nichtsnutz