RevEng Posted February 22, 2014 Share Posted February 22, 2014 (edited) Its an understatement to say that I'm not fond of reading through monospaced text docs. So I went ahead and converted the 7800 Software Guide into a PDF with a navigable index and proportional font for non-diagram text. I also added relevant TIA and 6532 info from the Stella doc, and an extra bit on reading two button joysticks.I found this version is a lot easier on the eyes and better for quick look-ups, so I figured I'd share. Feel free to report any errors here.7800 Software Guide updated.pdf Edited May 1, 2014 by RevEng 11 Quote Link to comment Share on other sites More sharing options...
PAC-MAN-RED Posted February 23, 2014 Share Posted February 23, 2014 "6532This chip is used only for I/O in 7800 mode, whereas in 2600 mode it also supplies access to all RAM andtimers. Its functions are more limited because its speed is not fast enough for normal operation. Anyaccess to this chip (joystick and switch I/O) will cause the microprocessor to slow to 1.19 MHz. Theports and switches connected through the 6532 are: joysticks (directional), pause, game select, gamereset, and difficulty switches. The 64532 can be used to generate output through the joystick ports aswell. For address information on 6532 ports and switches, refer to Appendix 2, Standard 7800 Equates." I'll keep going through the document and I'll Bold text to show possible additions, or things that may need attention/correction. 1 Quote Link to comment Share on other sites More sharing options...
PAC-MAN-RED Posted February 23, 2014 Share Posted February 23, 2014 "TIAThe TIA is only partly accessible in 7800 mode. While it occupies addresses x'0000' - x'003F' in 2600mode, only the section at x'0000' - x'001F' is available in 7800 mode. The only significant (useable)registers of these are the sound related registers and the input ports (fire buttons, paddle controllers).Any access to the TIA will cause the processor to slow from 1.79 MHz to 1.19 Mhz." 1 Quote Link to comment Share on other sites More sharing options...
PAC-MAN-RED Posted February 23, 2014 Share Posted February 23, 2014 "SALLY (6502)This is the microprocessor, which is also used in the ATARI 5200. The only thing special about theSally chip is that is has a HALT line, which allows the functionality described above." 1 Quote Link to comment Share on other sites More sharing options...
PAC-MAN-RED Posted February 23, 2014 Share Posted February 23, 2014 (edited) "GRAPHICSMARIA does not employ the concepts of players, missiles, and playfield, as do the 2600 and 5200.Instead MARIA uses an approach to graphics commonly used in coin-operated games. Each raster ofthe display may be thought of as a bit map. This map is contained in an area of the MARIA chip calledthe Line RAM. Information is first stored into the Line RAM, then later read from Line RAM anddisplayed on the screen.Consider for a moment just one raster of display. One would compose this raster's graphics by storingdata into Line RAM. This is done by specifying what data should be put at what horizontal location.Graphics may be specified in small pieces, and overlapped. The order in which pieces of a raster arespecified determines object priority with the last object specified on top.When graphics data is specified to be stored into Line RAM, it will reference any one of eight (8 ) colorpalettes. Each pixel of data will take on any one of three (3) colors from the specified palette, or may beturned off (transparent). Again, the Line RAM contains only one raster of graphics information. Thereare actually two Line RAM buffers. While one is being read (displayed), the other is being written fordisplay in the next raster. This means that the construction of graphics for a raster may take as long as, butno longer than, one raster, and that graphics must be stored into Line RAM on a raster by raster basis.The only limit to the number, and size of objects on one scan line is the mount of time it takes to loadeach into Line RAM, as all loading must occur during one scan line." Edited February 23, 2014 by PAC-MAN-RED 1 Quote Link to comment Share on other sites More sharing options...
PAC-MAN-RED Posted February 23, 2014 Share Posted February 23, 2014 "Display List ListMARIA locates the Display Lists by reading a Display List List (referred to as DLL from now on). Thislist is a series of 3 byte entries. Each entry points to a Display List. Included in each entry is a valuecalled OFFSET, which indicates how many rasters should use the specified Display List. OFFSET isdecremented at the end of each raster until it becomes negative, which indicates that the next DLLentry should now be read and used. Each time graphics data is to be fetched OFFSET is added to thespecified High address byte, to determine the accrual address where the data should be found. Thisallows one display list to specify many rasters of graphics. Without OFFSET the only approach tographics is to have a Display List for each raster, and a DLL for each Display List. Not only would thisuse a lot of RAM, but it would also take quite a bit of processing time to manipulate these Display Listswhen objects move. Because OFFSET is added to HIGH address byte, each raster of graphics for anobject must be separated by x'100' bytes, or one page. The group of rasters specified by one DLL entry is called a "zone." Again, the number of rasters in azone equals OFFSET+1. Larger zones mean less RAM is needed for DLLs, Display Lists andCharacter Maps (see DMA MODES below). But upon consideration of how to use zones, you willrealize that to achieve smooth vertical motion each stamp must be padded at top and bottom with zeros.For example, if the top raster of an object is to appear on the last line of a 16 high zone, it must have 15lines of zeros above it. If that object is 8 pixels (2 bytes) wide, and its top line of data is located atx'CF04', then you will need two bytes of zeros at x'D004', x'D104', x'D304',..., and x'DE04' (rememberthat OFFSET decrements). As this can add up to many pages of zeros, you can specify that MARIAshould interpret certain data as zeros, even if it isn't. This is called "Holey DMA" because DMA willsee "holes" in the data that aren't really there. This can be enabled and disabled on a zone by zone basisvia a DLL entry. Holey DMA has been aimed at 8 or 16 raster zones, but will have the same effect forother zone sizes. MARIA can be told to interpret odd 4K blocks as zeros, for 16 high zones, or odd 2Kblocks as zeros for 8 high zones. This will only work for addresses above x '8000'. This means thatthese blocks can hold meaningful code, or tables, or graphics data used in a zone where Holey DMA isnot on." 1 Quote Link to comment Share on other sites More sharing options...
PAC-MAN-RED Posted February 23, 2014 Share Posted February 23, 2014 "Display ModesThe normal display mode is 160 mode, where the screen is divided into 160 pixels horizontally.Typically graphics are done in 160x2 mode, where there are two color bits specified for each pixel, andthese two color bits refer to one of the eight palettes. Alternately, one may specify graphics in 160x4mode, where there are four color bits per pixel. In this mode, each byte of graphics data would specifyonly two (2) pixels of graphics. If higher resolution is preferred, 320x1 mode is the common choice,where the screen is divided into 320 pixels horizontally and each pixel has one color bit. A morecolorful 320x2 mode is also available with two color bits per pixel. Selection of a particular mode is accomplished through two separate operations: specification ofWRITE MODE, and specification of READ MODE. WRITE MODE is specified via the WMbit of an extended (5 byte) header, as described above. READ MODE is specified via the CTRLregister. Both of these specifications will remain in effect until respecified. WRITE MODE is notinitialized by MARIA on power-up, and must be initialized by the cartridge before any display occurs.The reason for specifying WRITE MODE via an extended header, is to allow the programmer tochange form 160x2 to 160x4 (or from 320x2 to 320x1, or vice-versa) during the DMA for a particularscan line. For more information about modes see CTRL under REGISTERS. 1 Quote Link to comment Share on other sites More sharing options...
PAC-MAN-RED Posted February 23, 2014 Share Posted February 23, 2014 "CHARBASE The CHARBASE register serves to specify the high address for any graphics data fetch in Character(Indirect) mode. As you recall, The Character Map (pointed to by the Header in the Display List)specifies the low address bytes of graphics data. Each of these low address bytes is concatenated withthe sum of CHARBASE + OFFSET, to give the full 16 bit addresses of where the graphics data shouldbe found[.] The CHARBASE register is WRITE ONLY." 1 Quote Link to comment Share on other sites More sharing options...
PAC-MAN-RED Posted February 23, 2014 Share Posted February 23, 2014 DPPLThis register is used to specify the low address byte of the Display List List. It to, is WRITE ONLY. 1 Quote Link to comment Share on other sites More sharing options...
PAC-MAN-RED Posted February 23, 2014 Share Posted February 23, 2014 "CTRLThe CTRL register is a WRITE ONLY register used to control many of the modes of MARIA. Throughthis register one can control whether the background color extends off the edge of the TV(horizontally), beyond the area where graphics may be positioned; or whether the background colorstops at the horizontal limits of graphics and this border area appears black. This border area is an areawhich appears undependably on various television sets. CTRL also specifies whether characters (in Character mode) are one or two bytes wide. That is, inCharacter (Indirect) mode, whether one, or two bytes of graphics data should be fetched at the addresspointed to by the Character Map entry and CHARBASE. The advantage of two byte characters is thatthe same number of pixels can be specified with half as many Character Map entries. The disadvantage is that when changing one character, twice as much of the screen is affected. This register also controls whether the color burst signal is generated or not. If color burst is turned off,the graphics are, of course, displayed in black and white, but with a greater clarity than if the gray scalecolors (x'00' - x'0F') were used. Another bit of CTRL enables "Kangaroo" mode which eliminates transparency, so that any pixel ofcolor "0" will be background color, rather than transparent. For the derivation of this name see theATARI coin-op game Kangaroo. DMA may be turned on or off via the CTRL register. At power-up DMA is off, and must be turned onby the cartridge. This should not be done until after DPPL and DPPH have been stored (so that DMAdoesn't try to read a DLL from an undefined location). DMA should be turned on DURING VBLANK,and never during the screen (rasters 16-258). If DMA is off the screen will continue to display thebackground color." 1 Quote Link to comment Share on other sites More sharing options...
PAC-MAN-RED Posted February 23, 2014 Share Posted February 23, 2014 Continued... 320A mode is a true 320x1 mode. Pixels that are "on" refer to color two (2) of the specified palette.Pixels that are off are transparent (or background color if "Kangaroo" mode is on). In 320B mode, whichis a 320x2 display mode, only the most significant palette bit is read. This means that either palette zero(0) of palette four (4) is used. If "Kangaroo" mode is off, transparency will work differently for modes.Consider a pair of 320-size pixels which make up one 160-size pixel. If either pixel of the pair is off, itwill not be transparent, but will take on background color instead. If both pixels are off, they will betransparent. With "Kangaroo" mode on, things work as one would expect them to work in this mode.Another factor concerning 320 modes is that the horizontal positioning still happens like 160 mode.This means that in 320 modes, objects can only be positioned in 2 pixel increments. Will continue tomorrow, need sleep now. 1 Quote Link to comment Share on other sites More sharing options...
RevEng Posted February 23, 2014 Author Share Posted February 23, 2014 Excellent! I'll fix those when you find all the typos or give up. 1 Quote Link to comment Share on other sites More sharing options...
PAC-MAN-RED Posted February 23, 2014 Share Posted February 23, 2014 Aye Skipper! Continued from the same area as my last two posts: "320C mode allows more colors than 320A, but cannot really be called 320x2. In this mode, some of thegraphics data goes to specifying palettes, which is somewhat non-standard. If a pixel is on, it is colortwo (2), and if it is off, it is transparent[,] or background color (same as 320A and 320B). The palette isdetermined by combining the most significant palette. The palette for the leftmost pixel is specified byP2,D3, and D2 (where P means a palette bit, and D means graphics data bit), and the graphics arespecified by D7. The next pixel right uses the same palette, and uses D6 for data. The next pixel rightuses a palette specified by P2, D1, and D0, and uses D5 for data. The rightmost pixel uses the samepalette, but D4 for data. The mapping for 320C mode is as follows:" Quote Link to comment Share on other sites More sharing options...
PAC-MAN-RED Posted February 23, 2014 Share Posted February 23, 2014 Overview of TIA SOUND In TIA there are two audio circuits for generating sound. They are identical but completely independentand can be operated simultaneously to produce sound effects through the TV speaker. Each audiocircuit has three registers that control a noise-tone generator (what kind of sound), a frequencyselection (high or low pitch of the sound), and a volume control. ToneThe noise-tone generator is controlled by writing to the 4 bit audio control registers (AUDC0,AUDC1). The values written cause different kinds of sounds to be generated. Some are pure tones likea flute, others have various "noise" content like a rocket[,] motor[,] or explosion. Even though the TIAhardware manual lists the sounds created by each value, some experimentation will be necessary to find"your sound". FrequencyFrequency selection is controlled by writing to a 5 bit audio frequency register (AUDF0, AUDF1). Thevalue written is used to divide a 30KHz reference frequency creating a higher or lower pitch of whatevertype of sound is created by the noise-tone generator. By combining the pure tones available from thenoise-tone generator with frequency selection[,] a wide range of tones can be generated. Quote Link to comment Share on other sites More sharing options...
PAC-MAN-RED Posted February 23, 2014 Share Posted February 23, 2014 Port A – Hand Controllers Port A is under full software control to be configured as an input or an output port. It can then be usedto read or control various hand-held controllers with the data bits defined differently depending on thetype of controller used. ... Joystick Controllers Two joysticks can be read by configuring the entire port as input and reading the data at SWCHAaccording to the following table: Data Direction Player----- -------- ------D7 right P0D6 left P0D5 down P0D4 up P0D3 right P1D2 left P1D1 down P1D0 up P1 (P0 = left player, P1 = right player)A "0" in a data bit indicates the joystick has been moved to close that switch. All "1's" in a player'snibble indicates that the joystick is not moving. ... Paddle (pot) Controllers Only the paddle triggers are read from the 6532. The paddles themselves are read at INPT0 thru INPT3of the TIA. The paddle triggers can be read at SWCHA according to the following table : Quote Link to comment Share on other sites More sharing options...
PAC-MAN-RED Posted February 23, 2014 Share Posted February 23, 2014 APPENDIX 1: 7800 MEMORY MAP The memory map of the 7800, graphically illustrated on the next page, is in many ways similar to thatof the 2600, with the addition not only of MARIA, but also of 4K of RAM. This RAM is shadowed(responds to other addresses) in zero, first, second, and third pages, the first two of these beingsignificant. You will notice the absence of the 128 bytes of 6532 RAM that make up zero page RAM inthe 2600. This is because of a speed discrepancy with the 6532. It's RAM has moved to an area in pagefour (4) and may not exist in future versions of the MARIA chip, so it should not be used. ... Where: X means "Don't Care[",] and A means the bits may be 1 or 0, but are not ignored. Entries 5 and 6indicate that pieces of RAM from x'1800' - x'27FF' appear in zero, and first pages. The last entryindicates that the last 2K block (x'2000' - x'27FF') is repeated at x'2800', x'3000', and x'3800' makingthis 6K area a series of 2K shadows. Quote Link to comment Share on other sites More sharing options...
PAC-MAN-RED Posted February 23, 2014 Share Posted February 23, 2014 APPENDIX 2: STANDARD 7800 EQUATES INPTCTRL EQU X '01' INPUT PORT CONTROL ("VBLANK" IN TIA) WOAUDC0 EQU X '15' AUDIO CONTROL CHANNEL 0 WOAUDC1 EQU X '16' AUDIO CONTROL CHANNEL 1 WOAUDF0 EQU X '17' AUDIO FREQUENCY CHANNEL 0 WOAUDF1 EQU X '18' AUDIO FREQUENCY CHANNEL 1 WOAUDV0 EQU X '19' AUDIO VOLUME CHANNEL 0 WOAUDV1 EQU X '1A' AUDIO VOLUME CHANNEL 1 WOINPT0 EQU X '08' PADDLE CONTROL INPUT 0 WOINPT1 EQU X '09' PADDLE CONTROL INPUT 1 WOINPT2 EQU X '0A' PADDLE CONTROL INPUT 2 WOINPT3 EQU X '0B' PADDLE CONTROL INPUT 3 WOINPT4 EQU X '0C' PLAYER 0 FIRE BUTTON INPUT WOINPT5 EQU X '0D' PLAYER 1 FIRE BUTTON INPUT WOBACKGRND EQU X '20' BACKGROUND COLOR R/WP0C1 EQU X '21' PALETTE 0 - COLOR 1 R/WP0C2 EQU X '22' - COLOR 2 R/WP0C3 EQU X '23' - COLOR 3 R/WWSYNC EQU X '24' WAIT FOR SYNC STROBEP1C1 EQU X '25' PALETTE 1 - COLOR 1 R/WP1C2 EQU X '26' - COLOR 2 R/WP1C3 EQU X '27' - COLOR 3 R/WMSTAT EQU X '28' MARIA STATUS ROP2C1 EQU X '29' PALETTE 2 - COLOR 1 R/WP2C2 EQU X '2A' - COLOR 2 R/WP2C3 EQU X '2B' - COLOR 3 R/WDPPH EQU X '2C' DISPLAY LIST LIST POINT HIGH WOP3C1 EQU X '2D' PALETTE 3 - COLOR 1 R/WP3C2 EQU X '2E' - COLOR 2 R/WP3C3 EQU X '2F' - COLOR 3 R/WDPPL EQU X '30' DISPLAY LIST LIST POINT LOW WOP4C1 EQU X '31' PALETTE 4 - COLOR 1 R/WP4C2 EQU X '32' - COLOR 2 R/WP4C3 EQU X '33' - COLOR 3 R/WCHARBASE EQU X '34' CHARACTER BASE ADDRESS WOP5C1 EQU X '35' PALETTE 5 - COLOR 1 R/WP5C2 EQU X '36' - COLOR 2 R/WP5C3 EQU X '37' - COLOR 3 R/WOFFSET EQU X '38' FOR FUTURE EXPANSION -STORE ZERO HERE R/WP6C1 EQU X '39' PALETTE 6 - COLOR 1 R/WP6C2 EQU X '3A' - COLOR 2 R/WP6C3 EQU X '3B' - COLOR 3 R/WCTRL EQU X '3C' MARIA CONTROL REGISTER WOP7C1 EQU X '3D' PALETTE 7 - COLOR 1 R/WP7C2 EQU X '3E' - COLOR 2 R/WP7C3 EQU X '3F' - COLOR 3 R/W SWCHA EQU X'280' P0,P1 JOYSTICK DIRECTIONAL INPUT R/WSWCHB EQU X'282' CONSOLE SWITCHES R/WSWACNT EQU X'281' I/O CONTROL FOR SWCHA R/WSWBCNT EQU X'283' I/O CONTROL FOR SWCHB R/W Quote Link to comment Share on other sites More sharing options...
PAC-MAN-RED Posted February 23, 2014 Share Posted February 23, 2014 (edited) APPENDIX 3: DMA TIMING There is some uncertainty as to the number of cycles DMA will require, because the internal MARIAchip timing resolution is 7.16 MHz, while the 6502 runs at either 1.79 MHz or 1.19MHz. As a result, itis not known how many extra cycles will be needed in DMA startup/shutdown to make the 6502 happy.It is even possible for the 6502 to be in the middle of a long (TIA or 6532) access when it is to behalted, so the uncertainty goes up to about 5 cycles.All times listed below refer to 7.16 MHz cycles. DMA startup 5-9 cycles Header (4 byte) 8 cycles Header (5 byte) 12 cycles Graphics Reads: Direct 3 cycles Indirect/1 byte 6 cycles Indirect/2 byte 9 cycles Character Map access 3 cycles Shutdown Times: Last line of zone 10-13 cycles Other lines of zone 4 - 7 cycles End of VBLANK is made up of a DMA startup plus a Long shutdown. DMA does not begin until 7 CPU (1.79 MHz) cycles into each scan line. The significance of this is thatthere is enough time to change a color, or change CTRL before DMA begins, and during HBLANK(before display begins). This figure should, however, be included in any DMA usage calculations.Another timing characteristic is that there is one CPU (7.16 MHz) cycle between DMA shutdown andgeneration of a DLI. Edited February 23, 2014 by PAC-MAN-RED Quote Link to comment Share on other sites More sharing options...
PAC-MAN-RED Posted February 23, 2014 Share Posted February 23, 2014 Okay, I'm done with it. Without being too nit-picky, and ignoring the appalling amount of misspellings of the word colour I managed to get through it all. Please double check everything, and I encourage others to jump in and have a go at fact checking this document. 1 Quote Link to comment Share on other sites More sharing options...
RevEng Posted February 23, 2014 Author Share Posted February 23, 2014 Thanks Illya! A couple needed slight tweaking for accuracy. (e.g. SWACNT is the Stella doc name for the register, so I instead I changed all SWACNT references to CTLSWA) Otherwise I've fixed it up as recommended and updated the first post. 1 Quote Link to comment Share on other sites More sharing options...
Jinks Posted February 24, 2014 Share Posted February 24, 2014 Did anyone ever try DM 0 or DM 1 just for shits? Or know what it does? It says for test mode. Quote Link to comment Share on other sites More sharing options...
CPUWIZ Posted February 24, 2014 Share Posted February 24, 2014 Did anyone ever try DM 0 or DM 1 just for shits? Or know what it does? It says for test mode. I wouldn't recommend it, it can fry some 7800's. Quote Link to comment Share on other sites More sharing options...
DanBoris Posted March 2, 2014 Share Posted March 2, 2014 Its an understatement to say that I'm not fond of reading through monospaced text docs. So I went ahead and converted the 7800 Software Guide into a PDF with a navigable index and proportional font for non-diagram text. I also added relevant TIA and 6532 info from the Stella doc, and an extra bit on reading two button joysticks. I found this version is a lot easier on the eyes and better for quick look-ups, so I figured I'd share. Feel free to report any errors here. 7800 Software Guide updated.pdf Nice work on cleaning up the guide! Can you add the information about the control register.... http://atariage.com/forums/blog/52/entry-5118-7800-control-register/ Quote Link to comment Share on other sites More sharing options...
RevEng Posted March 2, 2014 Author Share Posted March 2, 2014 Sounds good. I know the INPTCTRL register is in the TIA range... is it actually TIA that's behind the functionality, or is MARIA mapped over top of the TIA range? Or neither? Just trying to figure out to put it in the guide. Quote Link to comment Share on other sites More sharing options...
EricBall Posted March 3, 2014 Share Posted March 3, 2014 INPTCTRL is a write-only register mapped to $0000-$001F implemented by an external circuit (U11 on http://atariage.com/7800/archives/schematics_ntsc/Schematic_7800_NTSC_Low.html ) It is normally set (and locked) by the 7800 BIOS, so it's invisible to the program. Quote Link to comment Share on other sites More sharing options...
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