Using memory chip to control bankswitching?

[tokumaru]

I was looking at this page that shows how to build an Atari 2600 cart for use with an EPROM emulator. One interesting thing about it is that it uses an EEPROM to control the bankswitching and to invert A12. I really like the versatility of this, because you can easily simulate any hotspot bankswitching method you want, and you only need a chip twice the size of your program ROM (since the addressing space of the 6507 is twice the size of the range assigned to the ROM and the chip has to react to accesses to the whole addressing space).

 

Now that I think of it, you could even use the same technique to simulate other types of bankswitching, even the ones that use values from the address lines, as long as you can arrange it all into X inputs (X is the number of address lines in the EPROM/EEPROM/FlashROM) and 8 outputs.

 

Now, I remember having heard that using a ROM chip for this wasn't a good idea, because of how stable the data/address lines are/aren't, the chip driving its own address lines in a "loop", things like that. But apparently the guy did make a working cart this way, so that should prove that this is a valid option if you use fast enough chips, right? What do you think about this? How fast would you consider safe in this case?

[Rybags]

Unsure how that could work - data output from a chip should only be valid for the part of the cycle whilst the chip is selected and the OE line is activated.

Feeding back - looks like the data lines are going to high address lines, that would only work since the 6507 bus doesn't have those high lines so they're spare on the Eprom and can be used for other purposes.

 

I see the principal of the thing - Eproms have been used by people before to replace memory select logic that otherwise might had been performed by a PLA but they don't operate in a persistent mode, ie bank selection practically always has a latch type function where a bank is selected and remains there.

This scheme looks to be relying on that feedback situation to provide that latch functionality.

[tokumaru]

Unsure how that could work - data output from a chip should only be valid for the part of the cycle whilst the chip is selected and the OE line is activated.

Apparently, the ROM chip that controls everything is always enabled, and depending on the state of A12 it can enable or disable the program ROM.

 

Feeding back - looks like the data lines are going to high address lines, that would only work since the 6507 bus doesn't have those high lines so they're spare on the Eprom and can be used for other purposes.

The control ROM outputs the high address bits through its data pins, feeding them to the program ROM and back to itself, effectively selecting a bank in both chips. Each bank in the control ROM contains its own index in all bytes, except in the hotspot addresses, where indices of other banks are used to change banks.

 

I see the principal of the thing - Eproms have been used by people before to replace memory select logic that otherwise might had been performed by a PLA but they don't operate in a persistent mode, ie bank selection practically always has a latch type function where a bank is selected and remains there.

This scheme looks to be relying on that feedback situation to provide that latch functionality.

Yes, the ROM constantly feeds the current bank index back to itself, effectively keeping that bank selected until a hotspot is accessed and a new bank index is output to the high address lines. That's the part that looks weird to me, the chip controlling some of its own address lines through its data lines.

[Rybags]

Well... if it works... although I have no idea if Eproms were ever intended to be accessed in a persistent way like that.

 

Back to the speed thing - 2600 external to TIA all operates @ 1.19 MHz which was slow by 80s standards so it wouldn't be stressing the Eprom in that regard I should think.

[Carpenter]

Yes, the ROM constantly feeds the current bank index back to itself, effectively keeping that bank selected until a hotspot is accessed and a new bank index is output to the high address lines. That's the part that looks weird to me, the chip controlling some of its own address lines through its data lines.

 

This technique uses data feedback to keep states mapped by different areas of the memory space and it is well known in the digital world, specially by the old timers. No news here.

I implemented this kind of circuit to run F6 and F8 schemes and it worked fine. You only have to use fast memories, lets say 45 ns, to cope with instability, with a size twice or four times the 6507 ROM space (aka 8 or 16 kb) to store the states (or banks).

You can even remove the A12 line inverter chip (7404) because you can do this inversion in the data stored in the BS eprom. By doing this your cart basically will only have two components: the eproms.

At the time the VCs was designed, silicon space was expensive (memories and micro controllers/processors mainly) so all the bankswitching logic was implemented with discrete ICs in order to make the cart cheap to be manufactured.

In the present days you can find eproms very cheap or source them from electronic junk, so its cost doesn't matter anymore.

This makes very convenient the use of an extra eprom memory to store the BS logic for VCS carts.