Happy Warp 1050 7.1 Schematic

[reifsnyderb]

Hello,

 

Can anyone confirm if the second schematic, at the following link, works?

 

https://www.bighole.nl//pub/mirror/homepage.ntlworld.com/kryten_droid/Atari/800XL/1050/HAPPY/1050_happy_warp_drive.htm

 

Thanks!

 

Brian

 

[R.Cade]

Does there exist a gerbers file to get boards made?

[reifsnyderb]

36 minutes ago, R.Cade said:

Does there exist a gerbers file to get boards made?

Edit to add:  No gerbers are available that I know of.

 

I am thinking about making up boards.  My concern is they were drawn by Jerzy Sobola and, while he has done a lot of good with the schematics he's created,  I've noticed some of his schematics have errors.  I've gotten too many boards made to only have to hack them with cut traces and jumpers to get them to work.  (In all fairness, I also made up Atari 800 personality cards that had a fatal error in them and the part of the schematic, with the error, was from a version Atari's schematics.  Atari apparently found and fixed the error as another version, of the same schematic, doesn't have the error.)  So, if that schematic is good I will be a lot closer to getting a board made as I already have the schematic entered in KiCAD.

 

 

Edit to add:  I've modified the schematic to use a W65C02 processor.  Also, I'd make up a couple other modifications to allow for using newer chips...so they are easier to find.

 

Edited May 21, 2023 by reifsnyderb

[reifsnyderb]

<sigh>  Well, I can't say I am disappointed.  It turns out that pin 12 of U4 is supposed to be connected to A13.  However, A13 is not connected to anywhere else on the address bus.   😞

 

I am not sure if U4/pin 12 should be connected to the 6502 address bus or just connect it to +5vdc so the AND gate works.  Maybe I should install a solder jumper so both can be tried without having to cut traces and add wires later.    😞

 

 

 

 

 

https://www.bighole.nl//pub/mirror/homepage.ntlworld.com/kryten_droid/Atari/800XL/1050/HAPPY/1050_happy_warp_drive.htm

[reifsnyderb]

Ok, since this has been bothering me I made up an address map based on the schematic and compared it with the Altirra Hardware Manual's information.  With the exception of there being more RAM available, via the schematic, than what is listed in the Altirra Hardware Manual ($8000-$97FF), everything appears to fit.  (Maybe the Altirra Hardware Manual uses Happy source code or a disassembly to obtain the address range of the RAM?  I don't know.)

 

So, it appears that connecting U4/pin 12 to the 6502 A13 is the way to go.

 

Here's the map I came up with:

 

A read or write to the addresses for the "ROM Bank Switching" should change the bank.

 

Also, for the "Standard" 1050 map, all Hardware addresses have RIOT or 6810 RAM, not just at 0000-0FFF.

 

 

 

 

Edited May 21, 2023 by reifsnyderb

[+DrVenkman]

1 hour ago, reifsnyderb said:

Maybe the Altirra Hardware Manual uses Happy source code or a disassembly to obtain the address range of the RAM?  I don't know.

You should ask @phaeron - he’s generally very forthcoming about how he’s figured stuff out. 

[ijor]

14 hours ago, reifsnyderb said:

Edit to add:  I've modified the schematic to use a W65C02 processor.

 

Be aware that the CMOS 6502 variants are not 100% compatible with the old NMOS 6502 as used in the Happy.

 

Quote

With the exception of there being more RAM available, via the schematic, than what is listed in the Altirra Hardware Manual ($8000-$97FF), everything appears to fit.

 

The original Happy hardware had only 6K RAM, using three 2K RAM chips. At some point, when RAM prices were low enough, it seems it became cheaper to produce a board with a single 8K RAM chip. The official Happy software never uses the extra 2K RAM that was available in later boards.

Edited May 21, 2023 by ijor

[reifsnyderb]

59 minutes ago, ijor said:

 

Be aware that the CMOS 6502 variants are not 100% compatible with the old NMOS 6502 as used in the Happy.

It seems to be a common concern but I haven't seen any proof.  This page seems to contradict that there is any issue:  https://www.westerndesigncenter.com/wdc/AN-002_W65C02S_Replacements.php

Also, I've got a W65C02 running in an Atari 400 and have not used any transceivers.  In case there are problems, however, I put solder jumpers in the schematic to allow for either a 6502 or a W65C02.

 

59 minutes ago, ijor said:

The original Happy hardware had only 6K RAM, using three 2K RAM chips. At some point, when RAM prices were low enough, it seems it became cheaper to produce a board with a single 8K RAM chip. The official Happy software never uses the extra 2K RAM that was available in later boards.

That makes sense, then.

 

Edited May 21, 2023 by reifsnyderb

[reifsnyderb]

2 hours ago, DrVenkman said:

You should ask @phaeron - he’s generally very forthcoming about how he’s figured stuff out. 

I was thinking  about it but it's really not all that important.  What's more important is a good schematic.  After I made up the memory map I think I was able to verify how to fix the problem on the schematic.

[ijor]

10 minutes ago, reifsnyderb said:

It seems to be a common concern but I haven't seen any proof.  This page seems to contradict that there is any issue:  https://www.westerndesigncenter.com/wdc/AN-002_W65C02S_Replacements.php

Also, I've got a W65C02 running in an Atari 400 and have not used any transceivers. 

I'm talking about the software level, not the hardware level. This is not just a "common concern", it is well known and even officially documented in the datasheet that the , so called, "undocumented" NMOS 6502 instructions are not implemented. There are also other minor timing differences. They are just listed as improvements, and not as incompatibilities. Unfortunately both are true, they are improvements, but also bring some backwards incompatibilities.

 

[reifsnyderb]

Just now, ijor said:

I'm talking about the software level, not the hardware level. This is not just a "common concern", it is well known and even officially documented in the datasheet that the , so called, "undocumented" NMOS 6502 instructions are not implemented. There are also other minor timing differences. They are just listed as improvements, and not as incompatibilities. Unfortunately both are true, they are improvements, but also bring some backwards incompatibilities.

Sorry.  You are correct, the undocumented instructions are an incompatibility.  I wasn't considering them.

[reifsnyderb]

Here's the fixed Happy 7.1 schematic with A13 connected to the 6502 as per my understanding of how it's supposed to work.

 

[phaeron]

I ran a test on my Happy 1050, which appears to be genuine as it comes with the cheesy red void warranty tape over the chips:

• $0000-1FFF: 1050 hardware
• $2000-3FFF: bus conflict - hardware AND ROM
• $4000-5FFF: 1050 hardware mirror
• $6000-7FFF: bus conflict - hardware AND ROM
• $8000-9FFF: RAM
• $A000-BFFF: RAM mirror
• $C000-DFFF: open bus
• $E000-EFFF: ROM mirror
• $F000-FFFF: ROM

$A000-BFFF should be a bus conflict between the RAM and the ROM, but I'm not seeing that in testing. Not sure if there's something in the circuit that prevents this or if the RAM is just overpowering the ROM.

 

[Mathy]

Hello Brian

 

Maybe @guus.assmann can help you.

 

Sincerely

 

Mathy

 

[reifsnyderb]

56 minutes ago, phaeron said:

I ran a test on my Happy 1050, which appears to be genuine as it comes with the cheesy red void warranty tape over the chips:

• $0000-1FFF: 1050 hardware
• $2000-3FFF: bus conflict - hardware AND ROM
• $4000-5FFF: 1050 hardware mirror
• $6000-7FFF: bus conflict - hardware AND ROM
• $8000-9FFF: RAM
• $A000-BFFF: RAM mirror
• $C000-DFFF: open bus
• $E000-EFFF: ROM mirror
• $F000-FFFF: ROM

$A000-BFFF should be a bus conflict between the RAM and the ROM, but I'm not seeing that in testing. Not sure if there's something in the circuit that prevents this or if the RAM is just overpowering the ROM.

 

Do you know what version of Happy you have?  I've seen varying schematics for different versions of it.  Also, my belief is that with the 1050 ROM removed there shouldn't be bus conflicts.  Admittedly, this is the first time I've really looked at a Happy 1050...

 

Best Regards,

 

Brian

[phaeron]

12 minutes ago, reifsnyderb said:

Do you know what version of Happy you have?  I've seen varying schematics for different versions of it.  Also, my belief is that with the 1050 ROM removed there shouldn't be bus conflicts.  Admittedly, this is the first time I've really looked at a Happy 1050...

No, it's a bit of work to crack the 1050 open enough to check the inner PCB and I haven't gotten past removing the shield. I think it's the revised 8K model, but can't be sure without opening it up. Need to look up how to disassemble it.

 

The bus conflicts aren't with the 1050 ROM, they're either with the RIOT/6810/FDC or the Happy ROM. The $2000-3FFF and 4000-5FFF conflicts are due to the 1050 hardware activating on A15=0 while the ROM activates on A13=1. The RAM should conflict with the ROM at $A000-BFFF because the RAM decodes for A15=1 and A14=0, but no evidence of that in the readback. However, it doesn't make sense for the ROM to be enabled at 3/4 locations unless they snuck in an additional gate to disable the ROM on the RAM enable or used a different ROM chip that had a second output enable input.

 

Another piece of info I forgot to mention: no pullups on the data bus, so $C000-DFFF return floating bus data ($C0 and $D0 in my tests).

 

[reifsnyderb]

1 hour ago, phaeron said:

No, it's a bit of work to crack the 1050 open enough to check the inner PCB and I haven't gotten past removing the shield. I think it's the revised 8K model, but can't be sure without opening it up. Need to look up how to disassemble it.

 

The bus conflicts aren't with the 1050 ROM, they're either with the RIOT/6810/FDC or the Happy ROM. The $2000-3FFF and 4000-5FFF conflicts are due to the 1050 hardware activating on A15=0 while the ROM activates on A13=1. The RAM should conflict with the ROM at $A000-BFFF because the RAM decodes for A15=1 and A14=0, but no evidence of that in the readback. However, it doesn't make sense for the ROM to be enabled at 3/4 locations unless they snuck in an additional gate to disable the ROM on the RAM enable or used a different ROM chip that had a second output enable input.

 

Another piece of info I forgot to mention: no pullups on the data bus, so $C000-DFFF return floating bus data ($C0 and $D0 in my tests).

 

My thought is that if the Happy firmware addresses the Hardware/RAM only between 0000-0FFF, RAM from 8000-9FFF, and ROM at F000-FFFF there won't be any bus conflicts.  Otherwise, there certainly would be bus conflicts.  So, maybe that's the strategy in that if conflicted addresses are never called, there won't be a problem?

 

 

 

 

 

 

[phaeron]

1 hour ago, reifsnyderb said:

My thought is that if the Happy firmware addresses the Hardware/RAM only between 0000-0FFF, RAM from 8000-9FFF, and ROM at F000-FFFF there won't be any bus conflicts.  Otherwise, there certainly would be bus conflicts.  So, maybe that's the strategy in that if conflicted addresses are never called, there won't be a problem?

Correct, bus conflicts only occur when two devices drive the data bus in response to the same address. Which can't be a problem if that address never appears.

 

I disassembled the drive and it has the same PCB as in this thread:

Tracing the HART chip pinouts:

• pin 1 - A7
• pin 2 - A6
• pin 3 - A5
• pin 4 - A4
• pin 5 - A3
• pin 6 - A2
• pin 7 - A1
• pin 8 - A0
• pin 9 - D0
• pin 10 - D1
• pin 11 - D2
• pin 12 - grounded
• pin 13 - D3
• pin 14 - D4
• pin 15 - D5
• pin 16 - D6
• pin 17 - D7
• pin 18 - A11
• pin 19 - A10
• pin 20 - grounded
• pin 21 - A13
• pin 22 - A9
• pin 23 - A8
• pin 24 - Vcc

This matches with this alternate schematic, which confirms that pin 21 is an uninverted chip select:

 

However, I seem to recall that the flip-flops on the controller option board in that schematic are actually swapped. The controller option board affects two memory regions:

• Access to $4000-7FFF toggles the write protect state
• Access to $9800-9FFF or $B800-BFFF clears the write protect flip/flop, and if the switch is set to Slow, sets the 6502's V flag on every other access. (Note that this is the unused 2K of RAM address space in the 6K configuration.)

These address ranges are swapped from the wiring in the schematic, and I seem to recall that this was needed to get the diagnostic tests to pass. But it's been a while.

 

[reifsnyderb]

10 hours ago, phaeron said:

Correct, bus conflicts only occur when two devices drive the data bus in response to the same address. Which can't be a problem if that address never appears.

 

I disassembled the drive and it has the same PCB as in this thread:

Tracing the HART chip pinouts:

• pin 1 - A7
• pin 2 - A6
• pin 3 - A5
• pin 4 - A4
• pin 5 - A3
• pin 6 - A2
• pin 7 - A1
• pin 8 - A0
• pin 9 - D0
• pin 10 - D1
• pin 11 - D2
• pin 12 - grounded
• pin 13 - D3
• pin 14 - D4
• pin 15 - D5
• pin 16 - D6
• pin 17 - D7
• pin 18 - A11
• pin 19 - A10
• pin 20 - grounded
• pin 21 - A13
• pin 22 - A9
• pin 23 - A8
• pin 24 - Vcc

This matches with this alternate schematic, which confirms that pin 21 is an uninverted chip select:

 

However, I seem to recall that the flip-flops on the controller option board in that schematic are actually swapped. The controller option board affects two memory regions:

• Access to $4000-7FFF toggles the write protect state
• Access to $9800-9FFF or $B800-BFFF clears the write protect flip/flop, and if the switch is set to Slow, sets the 6502's V flag on every other access. (Note that this is the unused 2K of RAM address space in the 6K configuration.)

These address ranges are swapped from the wiring in the schematic, and I seem to recall that this was needed to get the diagnostic tests to pass. But it's been a while.

 

There are a lot of differences between this board and the board I have a schematic for.  I read that there are 2 different firmware revisions.  Could the early firmware revision work with your board and the later firmware revision work with the schematic I've got?

Edited May 22, 2023 by reifsnyderb

[reifsnyderb]

Well, I don't know if it will work and am having trouble finding the ROM, but here is the board I came up with...

 

 

There are solder jumpers to try both a 6502 and a W65C02.  Also, I added solder jumpers for the larger flash ROM chips just in case the smaller ones aren't available.

 

[+DrVenkman]

34 minutes ago, reifsnyderb said:

and am having trouble finding the ROM

There are at least some version(s) of the ROM floating around the forum (probably attached to posts in old Altirra threads) because I’ve got one for use simulating Happy drives in my emulated A8 setup, to match the Happy 1050’s I have connected to my main vintage A8 setup. 

 

EDIT: Check the files attached to this thread. I’m on my iPad right now (not my PC) so I can’t attach my own firmware files.

 

[Ricky Spanish]

1 hour ago, reifsnyderb said:

I don't know if it will work and am having trouble finding the ROM

Maybe here ?

 

[reifsnyderb]

1 hour ago, DrVenkman said:

There are at least some version(s) of the ROM floating around the forum (probably attached to posts in old Altirra threads) because I’ve got one for use simulating Happy drives in my emulated A8 setup, to match the Happy 1050’s I have connected to my main vintage A8 setup. 

 

EDIT: Check the files attached to this thread. I’m on my iPad right now (not my PC) so I can’t attach my own firmware files.

 

 

 

48 minutes ago, Ricky Spanish said:

Maybe here ?

 

 

Thanks!  I'll see if those will work.  The next time I order boards, I'll get a few of those Happy 7.1 boards I made up and test one out in one of my 1050's.

 

[+DjayBee]

15 hours ago, phaeron said:

The controller option board affects two memory regions:

• Access to $9800-9FFF or $B800-BFFF clears the write protect flip/flop, and if the switch is set to Slow, sets the 6502's V flag on every other access. (Note that this is the unused 2K of RAM address space in the 6K configuration.)

Does this mean that any software using this RAM area will play havoc with the write protection and (however this happens) the overflow flag of the CPU?

I am asking because @ijor stated that DiskMaster needs the whole 8 KB of RAM to operate.

If my fear is justified, DiskMaster cannot be used together with the Option Board.

[phaeron]

5 hours ago, reifsnyderb said:

There are a lot of differences between this board and the board I have a schematic for.  I read that there are 2 different firmware revisions.  Could the early firmware revision work with your board and the later firmware revision work with the schematic I've got?

As far as I know, there are only two known genuine firmware revisions verified by the diagnostics and there aren't dependencies on any particular hardware versions.

 

1 hour ago, DjayBee said:

Does this mean that any software using this RAM area will play havoc with the write protection and (however this happens) the overflow flag of the CPU?

I am asking because @ijor stated that DiskMaster needs the whole 8 KB of RAM to operate.

If my fear is justified, DiskMaster cannot be used together with the Option Board.

It's a possibility, though it's not clear if it would matter. Clearing the write protect flip-flop only has an effect if the firmware has inverted the WP state, and there may not be any code affected by the V flag. (I am not sure I have ever written any code using it, outside of CPU tests.) In any case, flipping the switches to fast and write unprotected should also work to override any of the side effects from the option board, with the only effect being that the write protect tabs would be ignored on the disks.