Tandon 810 won't boot or format

[TZJB]

9 hours ago, dukes909 said:

For what it's worth I downloaded a timing light app for my phone and used the pattern on the flyweel to set the speed to 300rpm and then 288rpm. No difference reading disks or booting from them. 🙄

 

Well done that's a great idea. At least you know it's no longer a disk speed issue.

Edited July 2, 2023 by TZJB

[+kheller2]

12 hours ago, dukes909 said:

Good question, I'd like to know as well. I wonder what is in the revision 3 version of the FSM or if it is available anywhere for download like R2.

Someone apparently just did this a few months back!  The page count seems low compared to what BEST states.  

 

 

[dukes909]

53 minutes ago, kheller2 said:

Someone apparently just did this a few months back!

Great find - thanks

[TZJB]

3 hours ago, kheller2 said:

Someone apparently just did this a few months back!  The page count seems low compared to what BEST states.  

 

 

 

Thanks to @drurywoodson we have an Atari 810 FSM Rev. 3. Well spotted @kheller2!

 

Disk read/writes are performed on the Atari 810 Analog Board which seems to connect to the read/write and erase heads via J209.

 

@dukes909, there are various head amplifier test points on that board in order to trace the frequency modulated read data signal, but make sure J209 is making good contact first.

 

Also do you have a head demagnetizer? It may be relevant.

 

Edited July 2, 2023 by TZJB

[dukes909]

3 hours ago, TZJB said:

but make sure J209 is making good contact first.

J209 is solid and I have continuity across each wire from the connector to the associated points in the head.

5 hours ago, TZJB said:

there are various head amplifier test points on that board in order to trace the frequency modulated read data signal

I need a little help there; am I looking for voltages there, or activity using a logic probe or something else? 

[dukes909]

5 hours ago, TZJB said:

isk read/writes are performed on the Atari 810 Analog Board which seems to connect to the read/write and erase heads via J209.

By the way, should there be a resistance reading between 3 & 4, 4 & 5, and 3 & 5 on the drive head connections at J209?  For one drive mechanism (I have 2 non-working 810's) I show all 3 of those as being open, no resistance/impedance. For the other drive mechanism I show 8ohms for 2 of them and 14ohms for the 3rd. It seems like the first drive mech is shot?...

[dukes909]

7 hours ago, TZJB said:

Also do you have a head demagnetizer?

Nope

[TZJB]

20 hours ago, dukes909 said:

J209 is solid and I have continuity across each wire from the connector to the associated points in the head.

 

That's great.

 

20 hours ago, dukes909 said:

I need a little help there; am I looking for voltages there, or activity using a logic probe or something else? 

 

The test points are intended for an oscilloscope of some description as these are analog waveforms that a logic probe would not detect.

[TZJB]

19 hours ago, dukes909 said:

By the way, should there be a resistance reading between 3 & 4, 4 & 5, and 3 & 5 on the drive head connections at J209?  For one drive mechanism (I have 2 non-working 810's) I show all 3 of those as being open, no resistance/impedance. For the other drive mechanism I show 8ohms for 2 of them and 14ohms for the 3rd. It seems like the first drive mech is shot?...

 

I wouldn't advise testing the resistance of the heads without a head de-magnetiser handy as a DC voltage may magnetise the heads. Has anyone had that experience or am I incorrect?

 

However J209 1&3 is the erase head and 4&5 is the read/write (R/W) head. Both should show a resistance reading as they are connected to the heads which consist of coils of wire.

 

J209 3 is also connected to the centre of the R/W head so should show a resistance reading of the two halves of the R/W head between 3&4 and 3&5. I think you may have proved this for one of your mechanisms and I would expect 4&5 to have the higher value.

 

If one mechanism has no head resistance it may well be open circuit causing the R/W issue.

 

What fault symptoms does the second 810 drive have? Can you swap mechanisms to make one good 810 drive?

Edited July 3, 2023 by TZJB

[dukes909]

2 minutes ago, TZJB said:

What fault symptoms does the second 810 drive have? Can you swap mechanisms to make one good 810 drive?

Unfortunately the 2nd drive has the exact same symptoms 😑 I've swapped all the boards with no progress.

[dukes909]

26 minutes ago, TZJB said:

 

That's great.

 

 

The test points are intended for an oscilloscope of some description as these are analog waveforms that a logic probe would not detect.

I have a scope that I am still learning to use!😛 But not sure what I am looking for. 

Edited July 3, 2023 by dukes909

[TZJB]

56 minutes ago, dukes909 said:

I have a scope that I am still learning to use! But not sure what I am looking for. 

 

I do have two Atari 810 disk drives of my own and they both worked the last time I tested them. One has an Archiver chip. I honestly can't remember what boards are inside them as they are in storage.

 

As a suggestion, with the 'good' mechanism but assuming you don't have a CPS Diagnostic Cartridge, have a look at page 3-14 of the Atari 810 FSM Ver. 3 which advises you what to set the 'scope to.

 

Page 8B-1 refers. Connect to TP2 and TP3 and try and read a disk. If it reads anything the waveform should show up here.

 

 

Edited July 3, 2023 by TZJB

[dukes909]

2 hours ago, TZJB said:

Connect to TP2 and TP3 and try and read a disk. If it reads anything the waveform should show up here.

I think what I have is correct?!

Edited July 3, 2023 by dukes909
2nd attachment

[TZJB]

9 hours ago, dukes909 said:

I think what I have is correct?!

 

That looks good. It is definitely reading the disk so brings into question what else is wrong.

 

Next check that TP1 is showing a signal as that is the next stage of amplification before the signal leaves the board.

 

After that I assume it goes on a cable to J102? The manual is not clear on this.

 

 

 

 

 

 

 

 

[dukes909]

14 hours ago, TZJB said:

Next check that TP1 is showing a signal as that is the next stage of amplification before the signal leaves the board.

 

The first image is the signal while the drive is trying to read the directory from DOS 2.0.

 

The second image is the signal once DOS "gives  up" and returns an ERROR 144 and the drive is not doing anything at all, so..is this a clock signal? I don't know what I'm looking at here.

14 hours ago, TZJB said:

After that I assume it goes on a cable to J102? The manual is not clear on this.

 

Yes to a header pin then wire then another header pin on the power supply board where it appears to go to the sideboard assembly pin 23 and then Z104?

 

The last 2 images are signals at pin 1 of Z104 during an attempted read, then the same pin while the drive is at rest.

[TZJB]

12 hours ago, dukes909 said:

The first image is the signal while the drive is trying to read the directory from DOS 2.0.

 

The second image is the signal once DOS "gives  up" and returns an ERROR 144 and the drive is not doing anything at all, so..is this a clock signal? I don't know what I'm looking at here.

Yes to a header pin then wire then another header pin on the power supply board where it appears to go to the sideboard assembly pin 23 and then Z104?

 

The last 2 images are signals at pin 1 of Z104 during an attempted read, then the same pin while the drive is at rest.

 

 

 

 

 

I think this looks correct. The signal waveform should become logic 1/0 after TP1 which it sort of is, buffered by R201/CR204/L102. Z104C pin 1 receives this data and inverts as it is an Exclusive NOR gate (NOT A+B) to drive the Z101B flip-flop and Z104B to clean it up. SAMS Computerfacts give some waveforms to check for, up to the 1771 FDC so follow the signal path to prove continuity. There are a few components here that might have failed but they are all physically quite large and accessible.

 

Unfortunately there seems to be a variety of circuit designs here so I am not sure which one is relevant to you.

 

I also just found out that the FD1771-11 model doesn't need -5V. Can you check yours please?

 

Edited July 5, 2023 by TZJB

[dukes909]

5 hours ago, TZJB said:

I also just found out that the FD1771-11 model doesn't need -5V. Can you check yours please?

Ok mine is the revision C sideboard that has the data separator board piggy-backed onto it, connecting via what is marked on the board as "A105" but on the schematic in the FSM r3 as J103.

5 hours ago, TZJB said:

to drive the Z101B flip-flop and Z104B to clean it up

First 2 scope pictures are of Z101B (pin4) read attempt, then with drive at rest.

Second 2 scope pictures are of Z101 pin 11 read attempt, then with drive at rest.

Third set is at pin 27 of J103 (where Z104 pin 11 leads to).

5 hours ago, TZJB said:

also just found out that the FD1771-11 model doesn't need -5V.

I have -5V at pin 1 of J103, +5V at pin 21, and +12V at pin 40.

 

On the daughterboard (data separator board), the pins on the chips are much more difficult to get to unless I rig up some header pins to connect from the power supply board to the sideboard.  

I looked at the SAMS Computerfacts at one time but it seems to be for a much earlier model than the one I have (I think theirs is the MPI drive and mine is the Grass Valley board Tandon).

Thank you for your continued help with this!

Edited July 5, 2023 by dukes909
Typo

[TZJB]

43 minutes ago, dukes909 said:

Ok mine is the revision C sideboard that has the data separator board piggy-backed onto it, connecting via what is marked on the board as "A105" but on the schematic in the FSM r3 as J103.

First 2 scope pictures are of Z101B (pin4) read attempt, then with drive at rest.

Second 2 scope pictures are of Z101 pin 11 read attempt, then with drive at rest.

Third set is at pin 27 of J103 (where Z104 pin 11 leads to).

I have -5V at pin 1 of J103, +5V at pin 21, and +12V at pin 40.

 

On the daughterboard (data separator board), the pins on the chips are much more difficult to get to unless I rig up some header pins to connect from the power supply board to the sideboard.  

I looked at the SAMS Computerfacts at one time but it seems to be for a much earlier model than the one I have (I think theirs is the MPI drive and mine is the Grass Valley board Tandon).

Thank you for your continued help with this!

 

You are welcome. Yes it's strange that SAMS is out of date as it is dated 1986.

 

Z101B pin 4 should be ground. Do you mean Z101B pin 5? Z101 pin 11 is used to supply the clock for the FD1772 on pin 24. Do you mean Z101B pin 1?

 

In any event J103 pin 27 looks good so the read circuit can be pronounced good for the most part. If you could get a reading from the FD1772 pins 26 & 27 it would verify it. They would be the same as A205 pins 6 & 3 which may just be reachable.

 

I can see you have a FD1772-01 so it needs -5V on pin 1. It may be worthwhile checking the states of FD1772 pins 1-20 as they are so accessible.

 

This is the full set of conditions from SAMS for the FD1772 so just check the ones you can reach for now. Pin 18 is unused in this application. Pin 26 is the floppy drive clock so maybe it should also be pulsing but you may have previously checked this from A205.

 

[dukes909]

2 hours ago, TZJB said:

Z101B pin 4 should be ground. Do you mean Z101B pin 5? Z101 pin 11 is used to supply the clock for the FD1772 on pin 24. Do you mean Z101B pin 1?

 

My mistake, I meant Z101B pin 1!

 

2 hours ago, TZJB said:

This is the full set of conditions from SAMS for the FD1772 so just check the ones you can reach for now.

Ok, I have a logic probe and can do this, maybe even get the other 20 pins if I move the analog board out of the way. What I don't know is - are these logic readings taken during the drive at rest or while it is attempting a read?

 

Also mine says FD1771B-01 which I assume is what you are referring to "FD1772"...?  Is this chip CMOS or TTL? I can't tell from the datasheet and my logic probe has a switch I have to choose from one or the other.

Edited July 5, 2023 by dukes909
additional info

[dukes909]

Ok, with mine set to CMOS and with the drive attempting a read, I get:

[TZJB]

18 hours ago, dukes909 said:

My mistake, I meant Z101B pin 1!

 

Ok, I have a logic probe and can do this, maybe even get the other 20 pins if I move the analog board out of the way. What I don't know is - are these logic readings taken during the drive at rest or while it is attempting a read?

 

Also mine says FD1771B-01 which I assume is what you are referring to "FD1772"...?  Is this chip CMOS or TTL? I can't tell from the datasheet and my logic probe has a switch I have to choose from one or the other.

 

I think our time zones are out of sync, and sorry for the typo there for FD1771. The 1772 is in the Atari ST...

 

The FD1771 is MOS/LSI with TTL compatible inputs and outputs.

 

CMOS generally have a greater range of voltage for logic signals. Up to 15V in fact, so TTL levels should be chosen.

 

Although the SAMS manual doesn't say, I think the drive should be at idle to take the readings.

 

17 hours ago, dukes909 said:

Ok, with mine set to CMOS and with the drive attempting a read, I get:

 

As you can see, the FD1771 pins are mainly all 1 to 1 to the A105/J103/P103 connector with only pins 26, 27 and 35 seperated (hence 'Data Seperator Board').

 

 

I have been through your readings:-

 

Pins 15-17 would normally control the stepper motor so will be slow pulses but are unused in this application. (6532 RIOT chip pins 18-22 PB2-PB5 are controlling this motor).

 

Pin 24 is the 1 MHz clock so doesn't look right. Maybe check it with the 'scope and also determine whether you are using A202 or Z101A to generate it.

 

Pin 25 is Ground so looks good.

 

Pin 30 is the Write Gate so looks good as you are not writing.

 

Pin 31 is Write Data and also looks good as you are reading.

 

Pin 35 is the index pulse and as you are spinning a disk it is expected to pulse.

 

Pin 38 is Data Request output and indicates that the Data Request contains assembled data while reading. It is an open drain output and is supposed to be held high with a 10K resistor (this may be internal within the 6532 pin 15 PA7, which is used as an input here).

 

For Pin 38 to be low while reading indicates there is no assembled data? Or is it inverted? Better check this one again with the 'scope.

 

 

Edited July 6, 2023 by TZJB

[+kheller2]

This couldn't be as simple as a bad PIA (RIOT) chip?

[dukes909]

7 hours ago, TZJB said:

CMOS generally have a greater range of voltage for logic signals. Up to 15V in fact, so TTL levels should be chosen.

 

Although the SAMS manual doesn't say, I think the drive should be at idle to take the readings.

Ok I will do this again with the drive at rest and with TTL selected on the logic probe.

 

7 hours ago, TZJB said:

For Pin 38 to be low while reading indicates there is no assembled data? Or is it inverted? Better check this one again with the 'scope.

I'll check this one and the clock line with the scope as well. 

 

Thanks again!

[dukes909]

1 hour ago, kheller2 said:

This couldn't be as simple as a bad PIA chip?

Is that the 6532?

[+kheller2]

21 minutes ago, dukes909 said:

Is that the 6532?

Yup, that's the RIOT (proper name) chip, although the docs say its a PIA -- which it is. Got a 1050 or 850 laying around?