1050 intrq from fdc v 810

[sup8pdct]

I am wondering if anyone has noticed this.

The 1050 has IRQ  of the 6532 (pin 25) connected to IP of FDC (pin 25) and to PA6 of the 6532 (pin 14). FDC INTRQ isn't connected to anything.

The 810 has IRQ of the 6532  connected to IP of FDC.  Pin 39 (INTRQ) of FDC goes to PA6 of the 6532.

 

I appears to me that it is a hardware error but it clearly doesn't affect anything, or the 1050 firmware was fixed to allow for this.

Why monitor the IP on the 6532 when it can be seen in status register of the FDC?

[phaeron]

/IP isn't an output from the FDC, it's an input -- it's how the FDC normally senses the index pulses from the drive mechanism. Except that the 810 and the 1050 don't use real index pulses, they use the RIOT to drive fake index pulses into the FDC. That's how they format tracks off-index and how the 810 fails out RNF within ~2 revs instead of 5. In fact, the 810 even relies on an undocumented feature of the RIOT to do this, that it will trigger an IRQ every 256 ticks after the initial timeout expires as long as the IRQ keeps getting cleared.

 

As for INTRQ, the 810 has a slow CPU (0.5MHz), so having the RIOT expose INTRQ on bit 6 for a BIT instruction is faster than polling bit 0 (BSY) on the FDC status register. The 1050's CPU runs faster at 1MHz, but it looks like its firmware doesn't bother checking for the end of operation interrupt and only does so at the end of a fake rotation through BSY, when the RIOT timer fires.

 

The PA6 connection on the 1050 is odd as I don't recall the 1050 firmware using it. The Happy 1050 firmware does, as it switches it to output to drive fake index pulses directly instead of relying on the RIOT timer to do it.

 

[sup8pdct]

16 minutes ago, phaeron said:

/IP isn't an output from the FDC, it's an input -- it's how the FDC normally senses the index pulses from the drive mechanism. Except that the 810 and the 1050 don't use real index pulses, they use the RIOT to drive fake index pulses into the FDC. That's how they format tracks off-index and how the 810 fails out RNF within ~2 revs instead of 5. In fact, the 810 even relies on an undocumented feature of the RIOT to do this, that it will trigger an IRQ every 256 ticks after the initial timeout expires as long as the IRQ keeps getting cleared.

 

As for INTRQ, the 810 has a slow CPU (0.5MHz), so having the RIOT expose INTRQ on bit 6 for a BIT instruction is faster than polling bit 0 (BSY) on the FDC status register. The 1050's CPU runs faster at 1MHz, but it looks like its firmware doesn't bother checking for the end of operation interrupt and only does so at the end of a fake rotation through BSY, when the RIOT timer fires.

 

The PA6 connection on the 1050 is odd as I don't recall the 1050 firmware using it. The Happy 1050 firmware does, as it switches it to output to drive fake index pulses directly instead of relying on the RIOT timer to do it.

 

I kinda knew about 1st paragraph.

 

Very interesting bit of info in 2nd and 3rd paragraph.

Still wondering if it was an oops in design. personally, i think it is.

 

[ijor]

1 hour ago, sup8pdct said:

Still wondering if it was an oops in design. personally, i think it is

You mean about the PA6 connected in the 1050? I would say that it is probably not a bug, and that it was by design to allow performing exactly what the Happy does. For some reason it wasn't finally used by the firmware, but that doesn't mean it was a hardware bug.

 

It is a pity that the original 1050 ROM sources never appeared. Possibly the comments on the source file would have given some clues. That's the difference between the original source and a reverse engineered one.

 

Edited October 4, 2023 by ijor