This is the result of think exercise to design a 2-D GPU similar to those used by 4th generation consoles (e.g. SNES, Genesis, TG16) but at HDTV resolutions.  Rule of thumb is to make it easy to program (i.e. minimum updates), while still being flexible.
 

Output is 1280x720 @ 60fps.  For reference, this has a 22.2usec line interval and 30 lines of VBLANK.

GPU contains internal 2.5Kbyte RAM for two 1280 x 8 bit line buffers (one is written while the other is read), reset to $00 at start of line.

GPU contains a single 256 x 24 bit CLUT (16 palettes of 16 colors, 24 bit RGB).  

GPU is connected to 1Mbyte 10ns RAM addressed as 8192 pages of 64 x 16bit words.  (Note: for sanity all data is little-endian, so bit 0 of byte 0 is bit 0 of word 0.)  GPU RAM is copied by DMA during VBLANK (up to 1024 pages per frame).  Page $0000 is typically set to all $0000.  DMA to pages $1FF8 - $1FFF also updates GPU registers / CLUT.

GPU registers:
$1FF8 [0..47]  CLUT [0..31] stored in packed format
$1FF8 [48..51] layer register [0..3]
$1FF8 [52..63] not used
$1FF9 [0..47]  CLUT [32..63]
$1FF9 [48..55] offset register [0..7]
$1FF9 [56..63] not used
$1FFA-F [0..47]  CLUT [64..255] (32 entries per page)
$1FFA-F [48..63] not used

layer register
[0..12] Zone list starting page number
[13]    not used
[14]    color 0 is 0=transparent, 1=opaque (taken from CLUT by palette)
[15]    zone type is 0=sprite, 1=tile

offset register
[0..7]  signed Y position offset
[8..15] signed X position offset

Rather than have a single table of sprite positions etc,  the GPU has 4 independent layers.  Each layer is described by a list of zone entries.  Each zone entry points to a list of tiles or sprites for 1 to 16 lines.  While this is more complex from a game programming perspective, it adds significantly more flexibility and dramatically increases the number of sprites the GPU can display.

The offset register is used to shift the position of multiple sprites by the same amount.

A single sprite / tile graphics block is 16 x 16 pixels and 4 bits per pixel, which is exactly 64 x 16 bit words = 1 page.  Color 0 is either transparent or opaque depending upon the layer register.  Pixels are stored in little endian raster order (i.e. bits 0..3 are top left pixel).

Tile Zone entry (48 bits / 3 words each, list may extend over multiple pages)
[0][0..11]   Tile List page number
[0][12..15]  16 - number of lines in zone
[1][0..11]   tile graphics block offset 
[1][12..15]  start line
[2][0..3]    start pixel
[2][4..9]    start tile (word offset of first tile in Tile List page)

Tile List entry (16 bits / 1 word each, list may extend over multiple pages)
[0..11]   graphics block index (added to graphics block offset to give page number)
[12..15]  palette

If number of lines in zone + start line > 16 then next graphics block will also be read.

Sprite Zone entry (32 bits / 2 words each, list may extend over multiple pages)
[0][0..11]   Sprite List page number
[0][12..15]  16 - number of lines in zone
[1][0..11]   sprite graphics block offset
[1][12..15]  not used

Sprite List Entry (48 bits / 3 words each, 21 entries = 1 page)
[0][0..9]    y position (0 - 1023 w/ wrap around 1023->0, 0 - 719 onscreen)
[0][10..12]  offset register number
[0][13..14]  y size - 1 (16,32,48 or 64 pixels high)  
[0][15]      y flip
[1][0..10]   x position (0 - 2047 w/ wrap around 2047->0, 0 - 1279 onscreen)
[1][11..12]  not used
[1][13..14]  x size - 1 (16,32,48 or 64 pixels wide)
[1][15]      x flip
[2][0..11]   graphics block index (added to graphics block offset to give page number)
[2][12..15]  palette

Graphics blocks for sprites larger than 16x16 are addressed sequentially in raster order