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The pic above was snapped while I was still working on the board. I sent Glenn finished snaps a moment ago.

 

Its not easy to see, but some of the changes are:

  • New microSD connector to allow hot swapping of cards
  • Overlapping SRAM footprints to allow multiple chips - 128K/256K/512K
  • Same CPLD but went to larger package - this allows more IO and the option to add the next sized CPLD for future development
  • The expansion ports now have protection resistors to protect cartridge and expansion devices agaist port configuration conflicts
  • EEPROM footprint is designed to accept chip from 128 bytes up to 32K of storage

Thats a few of the differences. Things got out of hand for about week as we let feature creep get the better of us, but we quickly culled it to what you see.

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