Possibly stupid question about vcs.h

[Devin]

I noticed that the vcs.h constants file uses "ds 1" rather than assigning the memory locations explicitly?

 

Wouldn't it be a tad safer to declare:

GRP0		= $1B

 

Rather than ...

GRP0		ds 1

[Cybergoth]

Don't think so. Those TIA registers seem to stay on their positions pretty reliable

[mos6507]

Don't think so. Those TIA registers seem to stay on their positions pretty reliable

 

I dunno. After 30 years they might want to move around a bit.

[SeaGtGruff]

I noticed that the vcs.h constants file uses "ds 1" rather than assigning the memory locations explicitly?

 

Wouldn't it be a tad safer to declare:

GRP0		= $1B

 

Rather than ...

GRP0		ds 1

The "vcs.h" file needs to stay more generic, so it's actually safer to *avoid* explicit memory locations. Due to the way the TIA is connected with the address lines of the 6507 CPU, the TIA registers are mirrored numerous times throughout the Atari 2600's address space. Even though the locations at $0000 through $002C are considered to be the "main" addresses, at least one bankswitching scheme ("3F" or TigerVision) uses the addresses below $0040 to trigger bank switches. For that reason, the TIA read/write registers need to be easy to relocate. If you look at the "vcs.h" file, you'll notice that it contains three special variables-- TIA_BASE_ADDRESS, TIA_BASE_READ_ADDRESS, and TIA_BASE_WRITE_ADDRESS. If you don't declare these variables in your code before including the "vcs.h" file, they will automatically default to $0000, which means the TIA registers will be defined from $0000 through $002C as expected. But if you want to write a program that will use the TigerVision bankswitching scheme, then you should do the following:

 

TIA_BASE_ADDRESS = $40; or $0040

  include "vcs.h"

That will cause the TIA registers to be defined from $0040 through $006C, so you can read from and write to the TIA registers without triggering any unwanted bank switches. You can also declare the TIA_BASE_READ_ADDRESS and the TIA_BASE_WRITE_ADDRESS separately, since they're mirrored differently-- for example, you could do the following:

 

TIA_BASE_WRITE_ADDRESS = $40; or $0040

TIA_BASE_READ_ADDRESS = $70; or $0070

  include "vcs.h"

Michael

[Devin]

The "vcs.h" file needs to stay more generic, so it's actually safer to *avoid* explicit memory locations. Due to the way the TIA is connected with the address lines of the 6507 CPU, the TIA registers are mirrored numerous times throughout the Atari 2600's address space. Even though the locations at $0000 through $002C are considered to be the "main" addresses, at least one bankswitching scheme ("3F" or TigerVision) uses the addresses below $0040 to trigger bank switches. For that reason, the TIA read/write registers need to be easy to relocate. If you look at the "vcs.h" file, you'll notice that it contains three special variables-- TIA_BASE_ADDRESS, TIA_BASE_READ_ADDRESS, and TIA_BASE_WRITE_ADDRESS. If you don't declare these variables in your code before including the "vcs.h" file, they will automatically default to $0000, which means the TIA registers will be defined from $0000 through $002C as expected. But if you want to write a program that will use the TigerVision bankswitching scheme, then you should do the following:

 

TIA_BASE_ADDRESS = $40; or $0040

  include "vcs.h"

...

 

Ah. Thank you. That does make sense. I was completely unaware that there was that type of functionality in the system. I'll use the standard vcs.h file for my project. Thanks Michael.

Edited January 1, 2008 by Devin

[supercat]

Ah. Thank you. That does make sense. I was completely unaware that there was that type of functionality in the system. I'll use the standard vcs.h file for my project.

 

Many systems behave that way. Essentially, what happens is that on every cycle the 6507 drives thirteen address lines and hopes that some device will recognize the pattern of bits and respond to it. Each device on the bus starts by looking at some of the address wires and deciding whether it should even consider doing anything that cycle. If it decides it should, it then looks at some more address wires to decide what to do.

 

The TIA write circuitry looks for address (0 xxxx 0xxx xxxx) and then uses the bottom six bits to decide what to do.

 

The TIA read circuitry looks for address (0 xxxx 0xxx xxxx) and then uses the bottom four bits to decide what to do.

 

The RIOT RAM looks for address (0 xx0x 1xxx xxxx) and then uses the bottom seven bits.

 

The RIOT I/O circuitry looks for address (0 xx1x 1xxx xxxx) and then uses the bottom five bits.

 

The "shadow" areas aren't really an intentional design feature. Rather, they exist because it's easier to ignore address bits than to decode them all. The only critical requirements are that (1) at most one device responds to any read cycle at a time by returning data, and (2) every device have at least some addresses where it will respond usefully without other devices responding in objectionable fashion.

[SeaGtGruff]

The RIOT I/O circuitry looks for address (0 xx1x 1xxx xxxx) and then uses the bottom five bits.

Actually, it depends on whether it's an input or output operation. As with TIA addresses, RIOT read and write addresses can overlap-- e.g., STA TIM8T and STA T1024T will set the timer to the requested number of 8-cycle or 1024-cycle periods, but LDA TIM8T and LDA T1024T will read the RIOT interrupt flags, because the addresses that are used for TIM8T and T1024T happen to be mirrors of TIMINT when a read operation is being performed.

 

Michael